nizam.ahmed Posted February 12, 2015 Report Share Posted February 12, 2015 Hi champs, I have a specific use-case where i would like to drive signals into the test-bench, but they are coming from different pthreads. I see that my implementation works. My deeper question is, is this allowed by the SystemVerilog LRM? In effect, the SystemVerilog and the simulation engine runs.... As it runs, asynchronously a pthread pushes a stimulus into the test-bench. We do the set_context and so on before driving into the system. But, still we would like to hear from horse-mouth! BR/Nizam Quote Link to comment Share on other sites More sharing options...
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