ljepson74 Posted June 18, 2014 Report Share Posted June 18, 2014 Emacs auto-indent for verilog-mode messes up when 'class' is used other than as an SV keyword. begin xyz.field1 = 1; xyz.field2 = 2; xyz.class = 3; xyz.field3 = 4; end Because the property name of an object (with instance name xyz above) is named "class", it screws up indentation. Is anyone here involved with Verilog/SV-mode for emacs or savvy enough to know how to resolve this? (Yes, this is perhaps on the wrong forum completely, but I think this likely would affect many users and is the most appropriate section of this forum.) From my .emacs file: ;;;;;;;;;;;;;;;;;;;;;; ;; Mac's Verilog Mode ;;;;;;;;;;;;;;;;;;;;;; (defun prepend-path ( my-path ) (setq load-path (cons (expand-file-name my-path) load-path))) (defun append-path ( my-path ) (setq load-path (append load-path (list (expand-file-name my-path))))) ;; Look first in the elisp directory which is ... (prepend-path "~/elisp") ;; Load verilog mode only when needed (autoload 'verilog-mode "verilog-mode" "Verilog mode" t ) ;; Any files that end in .__ should be in verilog mode ... (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.vh\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.hv\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.sv\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.svh\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.lib\\'" . verilog-mode) auto-mode-alist)) ;; Any files in verilog mode should have their keywords colorized (add-hook 'verilog-mode-hook '(lambda () (font-lock-mode 1))) ;; User customization for Verilog mode (setq verilog-indent-level 3 verilog-indent-level-module 3 verilog-indent-level-declaration 3 verilog-indent-level-behavioral 3 verilog-case-indent 2 verilog-auto-newline 0 verilog-auto-indent-on-newline t verilog-tab-always-indent t verilog-auto-endcomments t verilog-minimum-comment-distance 0 verilog-indent-begin-after-if t verilog-auto-lineup '(all)) After writing this, I posted on the correct forum, but will still post this one, to serve as a pointer to a great tool, verilog-mode. http://www.veripool.org/boards/16/topics/1372-Verilog-mode-auto-indent-messes-up-when-class-used-as-other-than-SV-keyword Quote Link to comment Share on other sites More sharing options...
ljepson74 Posted June 18, 2014 Author Report Share Posted June 18, 2014 Reply from other forum and a good point made: "This is not going to be fixed. Using keywords other than as keywords besides being a bad idea and not supported by many other tools, is too hard to support." http://www.veripool.org/boards/16/topics/1372?r=1373#message-1373 Quote Link to comment Share on other sites More sharing options...
uwes Posted June 18, 2014 Report Share Posted June 18, 2014 hi, keywords are keywords - you cant use them for identifiers. even if the language would support that it is nothing which helps to survive in your project.even if you find a tool which does that its very likely the next tool down the road will refuse to handle it. small example: typedef typedef; // forward define of a class typedef typedef foo; // is this an instance now(of the type typedef) or a forward typedef of foo ? Quote Link to comment Share on other sites More sharing options...
ljepson74 Posted June 20, 2014 Author Report Share Posted June 20, 2014 After further investigation..... 1) The offending code was generated from a non-SystemVerilog spec file 2) The offending code was CLASS, not class. The original example might have been more clear. I just retyped it rather than pasting the original offending code. As you can see, I hadn't tested the variable of uppercase/lowercase. *) I learned (remembered) SystemVerilog is case-sensitive. I learned from SV Spec 1800-2012.pdf section 5.6.2, Keywords: "All keywords are defined in lowercase only." *) The tool, correctly, does not issue an error or warning when uppercase is used. (When lowercase is used, an error is issued, as expected.) Emacs verilog-mode seems to be caps-insensitive, so had the 'error' in indentation when a non-keyword (CLASS in this case) is used. *) So, my original example masked the issue, as I incorrectly removed capitalization. Sorry for the confusion. And I agree completely with the verilog-mode folks' (and uwes') warning about keywords (and even close-to-keywords, I'll add) being used. 1) I'll point out to the verilog-mode folks the case issue I had and perhaps they will change their code. 2) I'll talk with our team about how we might avoid keywords across multiple languages in our generated code. I've learned a bunch from this small indentation issue that had been nagging me. thanks, all. Quote Link to comment Share on other sites More sharing options...
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