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Found 1 result

  1. Emacs auto-indent for verilog-mode messes up when 'class' is used other than as an SV keyword. begin xyz.field1 = 1; xyz.field2 = 2; xyz.class = 3; xyz.field3 = 4; end Because the property name of an object (with instance name xyz above) is named "class", it screws up indentation. Is anyone here involved with Verilog/SV-mode for emacs or savvy enough to know how to resolve this? (Yes, this is perhaps on the wrong forum completely, but I think this likely would affect many users and is the most appropriate section of this forum.) From my .emacs file: ;;;;;;;;;;;;;;;;;;;;;; ;; Mac's Verilog Mode ;;;;;;;;;;;;;;;;;;;;;; (defun prepend-path ( my-path ) (setq load-path (cons (expand-file-name my-path) load-path))) (defun append-path ( my-path ) (setq load-path (append load-path (list (expand-file-name my-path))))) ;; Look first in the elisp directory which is ... (prepend-path "~/elisp") ;; Load verilog mode only when needed (autoload 'verilog-mode "verilog-mode" "Verilog mode" t ) ;; Any files that end in .__ should be in verilog mode ... (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.vh\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.hv\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.sv\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.svh\\'" . verilog-mode) auto-mode-alist)) (setq auto-mode-alist (cons '("\\.lib\\'" . verilog-mode) auto-mode-alist)) ;; Any files in verilog mode should have their keywords colorized (add-hook 'verilog-mode-hook '(lambda () (font-lock-mode 1))) ;; User customization for Verilog mode (setq verilog-indent-level 3 verilog-indent-level-module 3 verilog-indent-level-declaration 3 verilog-indent-level-behavioral 3 verilog-case-indent 2 verilog-auto-newline 0 verilog-auto-indent-on-newline t verilog-tab-always-indent t verilog-auto-endcomments t verilog-minimum-comment-distance 0 verilog-indent-begin-after-if t verilog-auto-lineup '(all)) After writing this, I posted on the correct forum, but will still post this one, to serve as a pointer to a great tool, verilog-mode. http://www.veripool.org/boards/16/topics/1372-Verilog-mode-auto-indent-messes-up-when-class-used-as-other-than-SV-keyword
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