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Collector vs. monitor

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Here is a terminology question. Cadence uses the term, "collector" to refer to the transactor that sits on the bus and collects transactions based on signal changes, and then sends those transactions to a "monitor". This seems the opposite of how others use these terms, where the monitor is the low-level passive BFM, and it sends transactions up to a scoreboard collector, functional coverage collector, etc.

I could not find the term "collector" in the UVM documentation.


Chris Spear

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This term "collector" should be created by Sharon Rosenberg, the auther of the UVM book. its actually a part of the original monitor that in charge of facing singals and organizes them into atomic transactions. the monitor then in charge to combine atomic transactions into higher level transaction.

take the AHB for example, collector generates AHB Transfers and montiors generates AHB Burst, take USB for example, the collector generates USB packets and the monitors generates USB Transactions, each transaction may include 2-4 packets.

by the way, are you the author of "SystemVerilog for Verification"?

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The collector is an optional component of a UVC agent. It allows you to separate the signal-level monitoring and checking from the transaction-level monitoring and checking. This is similar to the sequencer/driver pair which handle the transaction-level and signal-level stimulus generation. We recommend that you use the split monitor (collector/monitor) if you plan to use transaction-level modeling or acceleration as alternate verification methods.


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