Best way of changing constraints from virtual sequence

[gaurav_brcm]

Hi All,
I have a basic question related to UVM methodology.
I have a virtual sequence , in which there are three child sequences .
Child sequences initially has some constraints , but now I want to change it from top level virtual sequence .
What is the recommended method of doing this , `uvm_do_with doesn't seem to be working.

Thanks a lot for help,
GG

[tudor.timi]

Depends on what you mean by changing the constraints. Using `uvm_do_with(...) will add the inline constraints on top of the ones already defined in the child sequences. If you want to disable a specific constraint you can do    child_seq.some_constraint.constraint_mode(0)

[gaurav_brcm]

Thanks a lot for your reply.

By changing constraint , I meant changing some values of field .

For eg :

class base_seq extends uvm_sequence; 

 packet pkt;

 `uvm_do_with (pkt.addr == a);

endclass

 

class top_seq extends uvm_sequence (virtual sequence)

  base_seq seq;

  `uvm_do_on_with(seq, p_sequencer.sqr { 

                               pkt.addr == b; } )

endclass

 

So in this case pkt.addr == b does not work and there is constraint failure.

 

What is the best way now ??

 

Thanks and Regards,

GG

[uwes]

hi,

 

if it is a constraint failure the tool will tell what kind of failure it is (not supported, contradiction,syntax error?....) . looks like in the posted code a colon is missing

 

/uwe

 

`uvm_do_on_with(read_byte_seq0, p_sequencer.seqr1, {read_byte_seq0.transmit_del == 0; })

 

 

[gaurav_brcm]

Hi uwes,

Thanks for reply.

The posted code is just for description.

The tool reports the contradiction error by showing the value of variable in child sequence and the value in the top sequence .

So what is the UVM way of changing the value in child sequences from virtual sequences ?

 

Regards,

GG

[tudor.timi]

As Uwe already mentioned, you might be using the macro wrong. Here is your first example fixed:

class base_seq extends uvm_sequence; 
 packet pkt;
 `uvm_do_with (pkt, { addr == a });
endclass

`uvm_do_with takes to arguments. The first one is the item or sequence. The second one is the constraint block. Conceptually this is equivalent to:

class base_seq extends uvm_sequence;
  packet pkt;

  // "unrolled" uvm_do_with (not the actual code)
  pkt = new("pkt");
  pkt.randomize() with { addr == a; };
endclass

If you get a contradiction it's because you are overconstraining, but this has nothing to do with UVM.