what is mean " no match for call to sc_core::sc_in<int>" ?

[carter]

Hi.

 

when i have make compile systemc the following code, Error was happened like this.

simple_fifo.cpp:45 error  no match for call to sc_core::sc_in<int>.

But i'm not sure. why this error happened?

My intend is like this.

 

reg [3:0] a;

always@(posedge clk)

begin

a <= a+ 1;

end

 

----------------------------------------------

 

[enchanter]

Maybe you can try to use:

 

    popo_out.write(popo_out.read() + popo_in.read());

 

in your while loop.

 

But another things I am not usre are:

 

1. If your popo_clk_gen will be triggered? The sensitive list seams no toggling at beginning.

2. Does the output (sc_out) can be used as sensitive signal?

[carter]

Maybe you can try to use:

 

    popo_out.write(popo_out.read() + popo_in.read());

 

in your while loop.

 

But another things I am not usre are:

 

1. If your popo_clk_gen will be triggered? The sensitive list seams no toggling at beginning.

2. Does the output (sc_out) can be used as sensitive signal?

1-> Did you mean that sc_start() is not exist?

2-> Actually, in verilog, it does'nt matter. But i not sure about it.

[enchanter]

1-> Did you mean that sc_start() is not exist?

2-> Actually, in verilog, it does'nt matter. But i not sure about it.

 

1 -> I don't mean sc_start(). I just don't know what's initial state of your sensitive list. Do they have any change at initial time to trigger your thread?

2 -> I think even in Verilog, it does matter. You logic is combinational logic, if the output can trigger the "+1" logic, you will have infinite loop, right?

[carter]

Does anyone know what am i check when this error happen" no match for call to sc_core::sc_in<int>" ?

And popo_out.write(popo_out.read() + popo_in.read()); is not work.

[carter]

1 -> I don't mean sc_start(). I just don't know what's initial state of your sensitive list. Do they have any change at initial time to trigger your thread?

2 -> I think even in Verilog, it does matter. You logic is combinational logic, if the output can trigger the "+1" logic, you will have infinite loop, right?

1 -> I don't mean sc_start(). I just don't know what's initial state of your sensitive list. Do they have any change at initial time to trigger your thread?

2 -> I think even in Verilog, it does matter. You logic is combinational logic, if the output can trigger the "+1" logic, you will have infinite loop, right?

1. -> i'm not sure, but it seems not exist. I think i need that. But i dont know, so would you please let me know?

2. -> yes right, infinite loop.

[dakupoto]

 

Hi.

 

when i have make compile systemc the following code, Error was happened like this.

simple_fifo.cpp:45 error  no match for call to sc_core::sc_in<int>.

But i'm not sure. why this error happened?

My intend is like this.

 

reg [3:0] a;

always@(posedge clk)

begin

a <= a+ 1;

end

 

----------------------------------------------

 

#include <systemc.h>

 

class popo_clk_gen : public sc_module

{

public:

sc_out<int> popo_out;

sc_in<int> popo_in;

SC_HAS_PROCESS(popo_clk_gen);

 

popo_clk_gen(sc_module_name name) : sc_module(name)

{

//SC_METHOD(test);

SC_THREAD(test);

sensitive << popo_in;

sensitive << popo_out;

}

void test()

            {

while(1) {

            {

            popo_out = popo_out + popo_in ;

wait();

            }

}

            }

 

};

 

int sc_main (int argc, char **argv)

{

sc_signal<int> popo_out;

sc_signal<int> popo_in;

 

sc_clock clk1("clk1", 20,SC_NS, 0.5,20,SC_NS);

popo_clk_gen pcg("pcg");

pcg.popo_out(popo_out);

pcg.popo_in(1);

 

return 0;

    }

 

Hello Sir,

There is unfortunately a major bug in your thread -- it does not

get triggered on any event. Please correct this first. Hope this

helps.

[carter]

Also, why value computed is not used?

Actually i dont know exactly what you mean.

[carter]

Now i still get interface fail.

Would you please let me know

How can i get interface?

[apfitch]

Hi Carter,

   can you post the exact error message, and the source of the line number (line 45?).

 

The obvious source of error to me is that you're trying to bind a constant value to a port with pcg.popo_in(1). That is probably where the error message comes from.

 

Secondly, as someone else may have said, you need to call sc_start() to make the simulation start.

 

regards

Alan

[carter]

..

[apfitch]

Try u_adder.pin.write(1).

 

Though that style of coding is strange. I would write a stimulus module and drive the stimulus from there - it's more code, but it's much easier to get working rather than trying to do stuff in sc_main.

 

See the example in

http://www.doulos.com/knowhow/systemc/tutorial.

 

By the way, sensitive_pos is deprecated, you should use

 

sensitive << p_clk.pos()

 

regards

Alan

[carter]

Try u_adder.pin.write(1).

Though that style of coding is strange. I would write a stimulus module and drive the stimulus from there - it's more code, but it's much easier to get working rather than trying to do stuff in sc_main.

See the example in

http://www.doulos.com/knowhow/systemc/tutorial.

By the way, sensitive_pos is deprecated, you should use

sensitive << p_clk.pos()

regards

Alan

Did you mean p_in instead pin?

Also, u_adder.pin.write(1) is error happened.

The error masage is "class sc_core::sc_in<int> has no member named 'write'

[carter]

Hello Sir,

There is unfortunately a major bug in your thread -- it does not

get triggered on any event. Please correct this first. Hope this

helps.

Dear dakupoto.

I modified code, but i have erreor. But i'm not sure.

So would you please let me know what is problem?

[apfitch]

Yes, sorry I meant p_in,

 

Alan

[carter]

Thank you