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Everything posted by carter

  1. Hi Does anyone have Makefile of at_example by doulos? If you can, could you please give to me about Makefile?
  2. Dear sir, When i have tried that, there's any have problem in PA. If you can, could you let me know the your xml?
  3. Hi When using the osci simulator it's seems that it need to define macro SC INCLUDE DYNAMIC PROCESS. But i'm not sure about what is mean "these particular socket"? What kind of socket? Also these are spawn dynamic processes. What is mean the dynamic processes is spawned? It seems related with between simple target socket and SC INCLUDE DYNAMIC PROCESSES. What is working sc include dynamic process macro?
  4. Hi I'm not sure to decide about what am i start at lt or at?
  5. Hi I willing to start verification. But i'm not sure which i have to use method whether systemC scv or UVM. Does anyone advice about what am i use and start from systemc or uvm for verification?
  6. Hi I want make break point into systemC OSCI code. I already know about i can use break point in visual c++. But i need that in linux. Is there any way how to make break point in systemC osci code in linux?
  7. I have a query, what is benefit to using user defined channel?
  8. should i make by class structure form for user define channel? If no, where i reference that?
  9. Thanks Alan, What kinds of caution should i catch up?
  10. Hi As i know, there are primitive channel and hierachical channel in systemC. But i'm not sure about should i know both of things? If you can, could you please let me know what thing is used for normally in company. Also second question is that can be possible use sc_signal and sc_fifo and sc_buffer in one module? If yes, what am i caution for using that in one module? Thanks
  11. As i know, when i use sc_signal , systemc have simulation deltas.But i not sure deltas. Where or how can i find deltas? and in tool? Would you means that deltas have same meanning between blocking and non blocking?
  12. So is delta time any affect to systemC simulation?
  13. Hi philipp.I'm not sure about "If you want to prepare the simulation without running it yet". Would you please let me know above case? I don't know the case about" to prepare the simulation without running" for what?
  14. Hi As i know, sc_initialize() is just work for systemc scheduler initialize. But i 'm not sure about what for use exactly? Would you please let me know what (why/when) i have to use this?
  15. Thanks When i change like this "digital_and1 (a_in , b_in , c_out);", anyway i can test passed. adder u_adder("adder"); u_adder(clk1, data , addr ); but i still have question , why i'm not have passed like following coded ?(port not bound..., no match for cal..bla~bla~) adder u_adder("adder"); u_adder.p_in(clk1); u_adder.q_in(data); ... ?
  16. Thanks but i'm not sure your answer. Is this right about should i use another module for test?
  17. hi can i make test bench code in sc_main() ? or i have to separate sc_main and test bench code? As i think, the test bench code is like this . sc_main () { ... adder u_adder("adder") u_adder.p_in(4); ... sc_start() sc_stop() ,,, } Error : complete binding failed : port not bound: port `adder.port_1' (sc_in)
  18. Hi. If port not bound code error happened, where am i check in this code which error : port not bound? so confused.
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