jsmith125x Posted February 11, 2014 Report Share Posted February 11, 2014 Hi, Is there similar in SystemC like last_value attribute in VHDL? I have a sc_logic signal and I'd like to determine a real negedge (1->0) but not from (X->0). How to do that? Quote Link to comment Share on other sites More sharing options...
ralph.goergen Posted February 11, 2014 Report Share Posted February 11, 2014 Hi. Accessing the last value is not possible in SystemC out of the box. I see two possibilities here. First is to implement your own signal class derived from sc_signal. Then, you can override the update method, store the last value and add your own methods to access this value. Second, you may use dynamic sensitivity. If the value of the signal is '1', you can wait for the 'negedge_event' directly. Otherwise, you can wait for a 'posedge_event' first and then wait for the following 'negedge_event'. Greetings Ralph Philipp A Hartmann 1 Quote Link to comment Share on other sites More sharing options...
dakupoto Posted February 12, 2014 Report Share Posted February 12, 2014 Hi, Is there similar in SystemC like last_value attribute in VHDL? I have a sc_logic signal and I'd like to determine a real negedge (1->0) but not from (X->0). How to do that? Hello Sir, One option would be to have a module thread that is sensitive to ALL changes in e.g., an input signal. Then each time a new value is read in, compare it with the previous value of the same signal variable,and take appropriate action. The current value of the signal variable is stored, after all processing is complete, as the last value, to be used for comparison for the next value of the signal variable. A very intuitive, straightforward approach. Please note that VHDL has been designed with the very aim of simulating hardware, and so there would not be any direct parallels with C++ features - but workarounds are always possible. Hope that helps. Quote Link to comment Share on other sites More sharing options...
ralph.goergen Posted February 12, 2014 Report Share Posted February 12, 2014 Hi. One option would be to have a module thread that is sensitive to ALLchanges in e.g., an input signal. You have to be careful with this solution because it adds one delta cycle to the signal flow. This may not be a problem, but, e.g., with clock signals, this may lead to erroneous behavior. Using immediate notification possibly solves this problem, but immediate notification has its own pitfalls. Greetings Ralph Quote Link to comment Share on other sites More sharing options...
David Black Posted February 12, 2014 Report Share Posted February 12, 2014 I think deriving your own specialized signal class is the best solution. This is similar to Ralph's suggestion, but restricted to sc_logic. It will make the coding go faster. struct my_signal : sc_signal<sc_logic> { // Override appropriate methods void write(...) { } void update() { ... } private: sc_logic prev; } Quote Link to comment Share on other sites More sharing options...
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