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jsmith125x last won the day on February 21 2014

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  1. In our VHDL engine we are creating rollback points during simulation. This saves all VHDL data (incremental), including process states, stacks, signals, time etc. When the analog engine requires rollback (because of convergence problem), the VHDL engine select the proper rollback point and restores the whole engine to this point (process states, stacks, signals, time etc).
  2. (1) The analog engine is our analog engine (SPICE basically). The VHDL and analog co-simulation is working properly. Now we'd like to extend to handle SystemC digital models. Our co-simulation engine uses rollback currently. (2) This engine uses rollback also? http://www.systemc-ams.org/
  3. Hi, Could you give me some guidelines on systemc analog co-simulation? We are currently using rollback with VHDL analog co-simulation but rollback with SystemC is almost impossible.
  4. Hi, Is there similar in SystemC like last_value attribute in VHDL? I have a sc_logic signal and I'd like to determine a real negedge (1->0) but not from (X->0). How to do that?
  5. Hi, What is that in SystemC? a <= b after 10 ns; -- a and b are signals
  6. Hi, I'd like to run sc_start(duration) but to stop when a node change. Nodes are the out ports at top level. Is there this feauture or could you give me guidlines how to implement it?
  7. For some reason I can not embed the main program to the systemc model dll. Can I start the systemc simulation in a thread?
  8. Hi, I have compiled the systemc model to a dll, now I'd like to run the simulation from an another module (.exe) step by step. For example run the simulation to 20ns then run the simulation to 40ns, when the user press a button. Which is the best way? The problem sc_main is exit once the simulation is started.
  9. I have a simulation time point when the user press the switch. How to send an event to the kernel?
  10. I'm trying to implement an interactive digital simulator using SystemC. The user can place switches, gates etc. and can simulate the circuit. I have some problem with switches. Assume there is a circuit containing a "clock" an "and gate" and a "switch". The switch can switch from the H and L states to the output. By default it is low state, when the user press the switch its output goes to the high state. The and gate's inputs connected to the clock and to the switch. The circuit is converted to its SystemC representation (except the switch). The simulation runs endless, because of the clock. How to handle pressing the switch in the SystemC engine? I assume I have to send an event manually to the kernel. How to do that? Im running the SystemC simulation through a dll (the SystemC representation of the circuit is compiled to a dll).
  11. My problem, I cannot connect a clock to my and gate module. I have got compiler errors. int sc_main(int argc, char* argv[]) { sc_signal<sc_logic> q,c,b,a; sc_signal<sc_logic> N2_1,N0; sc_clock clk("clk", 1, SC_US, 0.5, 0, SC_US, true); org U1("U1"); U1.I1(clk); U1.I2(c); U1.Q(q); andg U2("U2"); U2.I1(a); U2.I2(; U2.Q(N2_1); testbench TB("TB"); TB << q << c << b << a; monitor MON("MON"); MON << q << c << b << a; sc_start(10, SC_US); return 0; } ... #ifndef andgH #define andgH #include "systemc.h" SC_MODULE(andg) { sc_in<sc_logic> I1, I2; // input pins sc_out<sc_logic> Q; // output pin o void proc() { Q = I1 & I2; } SC_CTOR(andg) { SC_METHOD(proc); sensitive << I1 << I2; } }; #endif Or If not works how could I make a clock like in vhdl. process begin clk <= '0'; wait for 1 us; clk <= '1'; wait for 1 us; end process;
  12. Hi, How to convert sc_bool to sc_logic? I have a clock which is connected to an and gate. The gate accepts sc_logic signals.
  13. ...\\notg.h(11): error C2678: binary '~' : no operator found which takes a left-hand operand of type 'sc_core::sc_in<sc_dt::sc_logic>' (or there is no acceptable conversion) [...\\systemc_model.vcxproj] #ifndef notgH #define notgH #include "systemc.h" SC_MODULE(notg) { sc_in<sc_logic> a; // input pins sc_out<sc_logic> o; // output pin o void proc() { o = ~a; } SC_CTOR(notg) { SC_METHOD(proc); sensitive << a; } }; #endif
  14. I have got error message for ~ operator too.
  15. Hi, How to implement a simple not gate with sc_logic type inputs? The ! operator is not defined for this type.
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