vhdl after construct

[jsmith125x]

Hi,

 

What is that in SystemC?

a <= b after 10 ns;
-- a and b are signals

[apfitch]

There's no easy equivalent. You could do

int atemp;  // or whatever data type a and b are

void proc() {
    while (true) {
         atemp = a.read();
         wait (10, SC_NS);
         b.write(atemp);
    }
}

SC_THREAD(proc);
sensitive << b;

You might possibly be able to build some kind of wrapper around sc_event_queue

 

regards

Alan

[David Black]

I've often thought of writing a delayed assignment channel for SystemC. Probably just a new signature for sc_signal::write(...).

 

Of course that begs the question of transport vs inertial delay, which would be interesting to use. I think both are likely to have their uses.

 

Perhaps:

 

template<typename T>

class sc_signal_delayed

: public sc_core::sc_signal<T>

{

    ...

    void write(const T& value, sc_time delay, bool transport=true) { ...details left to the implementor... }

};