end of test methodology in uvm

[uwes]

hi,

attached is an example showing howto use the end of test facilities in uvm. also included are some examples of messages written after the run phase or really just before the simulator exits. i usually do not call global_stop_request() or $finish directly in order to give other components the time they need to shutdown gracefully.

if one requires specific messaging at the end of test usually the phases check() and/or report() are good to use. in case of a very final (after all uvm phasing) message before quit i would suggest a final block.

the functions for reporting:

uvm_report_(info|warning|error|fatal)(<tag>,<msg>,<severity>)

objections:

<objection.(raise|drop)_objection();

regards

/uwe

(the right way to go are objections - as in ovm)

// @test:
module test10;
   import uvm_pkg::*;
`include "uvm_macros.svh"

   class lower_comp extends uvm_component;
       function new(string name, uvm_component parent);
           super.new(name,parent);
       endfunction
       task run;
           fork
               repeat(3) #40 uvm_test_done.raise_objection(this);
               repeat(3) #61 uvm_test_done.drop_objection(this);
           join
       endtask
   endclass

   class test extends uvm_component;
       lower_comp tc;
       `uvm_component_utils(test)

       function new(string name, uvm_component parent);
           super.new(name,parent);
           tc = new("tc", this);
       endfunction
       virtual task all_dropped (uvm_objection objection, uvm_object source_obj, 
               string description, int count);
           uvm_report_info("MSG","message",UVM_NONE);
           assert(2==2) else uvm_report_error("MSG","some error message",UVM_NONE);
       endtask
       function void report();
           $display("here we are in the report phase - and simulation has ended");
       endfunction

   endclass

   initial run_test("test");

// this is really at the end of everything
final begin
$display("this is really the end of all");
end

endmodule

Edited July 9, 2010 by uwes

[enchanter]

Thanks for the way to interpreted with example. But I notice that you are using uvm_test_done instead of phase. Could I know what's the difference between them?

I just try the hello_world example in UVM-1.1.

That use specific time "1us" to end the test. I try to use raise/drop objection in both producer/consumer/top modules. But I got timeout of 9200 seconds error.

Can anyone show me how should I end the test without put specific time in it?

thanks.

[Erling]

I don't think this is a good way to handle end of test. It is based on a deprecated feature and can also bring the entire test environment to a crawl if the lower_comp has frequent objection raise/drop calls, because the lonely simulation core will waste cycles on forked mountain climbing for no valid reason. A better approach, in my opinion, is to hide the entire objection mechanism in a base class common to all tests, so that individual tests comes ready to live, not die, and combine this with quick phase locking to protect critical regions in the test environment from abortive end of phase.

Erling

[uwes]

hi,

couple of things

- the original post is quite some old post, slightly mixing old and new style phasing/phase progression.

- the uvm_test_done objection is basically the objection to end the run phase. (using the uvm_test_done objection is the ovm/uvm10ea style while objecting the appropriate phase is the current way)

- 9200sec usually indicates that the run didnt end with consensus to stop earlier. that means that most likely there is an objection pending.

- looking at the uvm example i see

  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    uvm_top.print_topology();
    #1us;
    phase.drop_objection(this);
 endtask

so a wait of 1usec then a drop and the simulation should stop - and thats what i see:

UVM_INFO ../../../src/base/uvm_objection.svh(1120) @ 1000 ns: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

BTW: no matter what you do, how you encapsulate it and optimize it with a companion object like erling suggests the main thing is that at least ONE needs to object an end of phase to keep your simulation running. if NO objection is pending the phase progression goes forward and finally ends simulation via extract, report,check

[enchanter]

hi,

couple of things

- the original post is quite some old post, slightly mixing old and new style phasing/phase progression.

- the uvm_test_done objection is basically the objection to end the run phase. (using the uvm_test_done objection is the ovm/uvm10ea style while objecting the appropriate phase is the current way)

- 9200sec usually indicates that the run didnt end with consensus to stop earlier. that means that most likely there is an objection pending.

- looking at the uvm example i see

task run_phase(uvm_phase phase);
     phase.raise_objection(this);
     uvm_top.print_topology();
     #1us;
     phase.drop_objection(this);
  endtask

so a wait of 1usec then a drop and the simulation should stop - and thats what i see:

UVM_INFO ../../../src/base/uvm_objection.svh(1120) @ 1000 ns: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

BTW: no matter what you do, how you encapsulate it and optimize it with a companion object like erling suggests the main thing is that at least ONE needs to object an end of phase to keep your simulation running. if NO objection is pending the phase progression goes forward and finally ends simulation via extract, report,check

My question is if I can try to not use `#1ns` in the "hello_world" example?

Because I think in some cases, I can't predict how long the simulation is needed. And I also want it to be ended as soon as possible.

I tried the

task run_phase(uvm_phase phase);
     phase.raise_objection(this);
     uvm_top.print_topology();
     phase.drop_objection(this);
  endtask

It doesn't work very well. I also put the raise/drop inside the producer and consumer. I got timeout.

[uwes]

hi,

the 1us in the example do not need to be there (its just an example to reach consensus after 1us).

> I can't predict how long the simulation is needed

thats when you need objections

> It doesn't work very well

what does that mean? what behaviour do you see? for me this looks good.

/uwe

[chenyong]

Hi,

I know "set_drain_time" could be used to extend simulation time after objection is dropped. Does this method work for you?

CY

[steve]

Hi Uwe,

Thanks for the code snippets. I also found a good DVCON paper on UVM test termination here:

http://www.sunburst-design.com/papers/CummingsDVCon2011_UVM_TerminationTechniques.pdf

One issue I have encountered is test termination in a UVM environment that is entirely passive (the test is driven by a legacy top-level environment). Here, I raised an objection in the uvm_test class, but had to create an "end_of_test" signal in the bench in order to drop the objection.

Is there a more elegant way of doing this?

In the test class:

task my_test_base::run_phase(uvm_phase phase);
  ...
  uvm_test_done.raise_objection(this);     // This objection is dropped by the verilog testbench
endtask: run_phase

In the testbench:

task t_sim_end;
        end_of_test = 1'b1;
endtask

always  @(end_of_test) begin
  if (end_of_test)
    uvm_test_done.drop_objection(uvm_top.find("*uvm_test_top"));
end

[Erling]

You could try to have the verilog testbench post an event, and then have the top level test wait for it, for example:

task my_test_base::run_phase(uvm_phase phase);
  phase.raise_objection(this);
  @end_of_test;
  phase.drop_objection(this);
endtask: run_phase

Erling

[uwes]

hi,

why not simply:

// raise somewhere

uvm_pkg::uvm_test_done.raise_objection(uvm_pkg::uvm_top);

// drop somewhere

uvm_pkg::uvm_test_done.drop_objection(uvm_pkg::uvm_top);

[steve]

Thanks, that's perfect!

Steve

[IChip]

Hi uwes, Why not works as codes written below:

class env extends uvm_agent;

...

task run_phase(uvm_phase phase);

uvm_pkg::uvm_test_done.raise_objection(uvm_pkg::uvm_top);

endtask

task main_phase(uvm_phase phase);

`uvm_info(get_name(),"main_phase.",UVM_NONE)

endtask

endclass: env

initial begin

run_test("env");

#1us;

uvm_pkg::uvm_test_done.drop_objection(uvm_pkg::uvm_top);

end

[uwes]

hi,

run_test never returns (it ends with a timeout).the #1us + drop are never executed. you could write it as

initial run:test("env");

initial #1us uvm_pkg::uvm_test_done.drop_objection(uvm_pkg::uvm _top);

/uwe

[IChip]

hi,

run_test never returns (it ends with a timeout).the #1us + drop are never executed. you could write it as

initial run:test("env");

initial #1us uvm_pkg::uvm_test_done.drop_objection(uvm_pkg::uvm _top);

/uwe

Thanks, uwes