Accessing an Output port through Backdoor using UVM Register Model

[vismayp]

Hi Guys,

  I am using UVM Register model to mimmick RTL's register implementation. Some registers are not implemented in RTL which are going to be connected to output port of some other module.

I have got a HDL path of register as an output port declaration of some module.

 

Something like:

   The HDL path is: "tb_top.dut_u.interrupt_module_u.o_ext_interrupt"

 

o_ext_interrupt is declared as output port inside interrupt_module, which is not connected to any other wire or register.

 

Can this output port's value be changed by writing to it via UVM BACKDOOR ? 

 

I am using following API:

register_name.write(status,data,UVM_BACKDOOR,default_map);

 

I dont see any change in value in the register. I think it is happening because the destination (o_ext_interrupt) is output of the module.

 

I am using Cadence's simulator: irun.

 

Please help if anyone is aware of such issue.

 

Regards,

Vismay.

[David Black]

If the port is not connected, it is likely declared as a wire rather than a var'iable. I would expect you would need to force (uvm_hld_force) the the port rather than just a simple write. If you are trying to do this via a register, then you will need to query the register for the path to that bit in order to use force (uvm_reg::get_full_hdl_path). You will also need to learn about uvm_hdl_path_concat. These are all documented in the class reference.