How to verify reset processing with UVM?

[nslmike]

Hello everybody.

 

How to verify RTL's reset processing? It seems, there are no examples to demonstrate it.

My RTL design is optimized with synchronuous reset, but resest signal do not feed all registers (for example no need to reset shiftregs in many cases, but resettig FSM is a must). I have already found some bugs in reset processing, but I want to do it with UVM. What is a way to do it?

One more agent, including driver & monitor for reset? One more seq_item for it?

[bhunter1972]

I wrote a paper on this a while back:

http://www.synopsys.com/news/pubs/snug/2013/silicon-valley/ma4_hunter_paper.pdf

[nslmike]

Thank you.

Is it available only for Synopsys customers? (Registering on synopsys.com require having a Site ID and a license file)

[bhunter1972]

Thank you.

Is it available only for Synopsys customers? (Registering on synopsys.com require having a Site ID and a license file)

So sorry! I was not alerted by the system that you had replied to this topic.

 

I'm not really sure if it's available or not, but send me a message and I'll send you a pdf.

[Roman]

I believe follow topic could address your problem well.

 

"Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package" 

 

http://www.cadence.com/Community/blogs/fv/archive/2014/02/26/resetting-your-uvm-sytemverilog-environment-in-the-middle-of-a-test-_2D00_-introducing-the-uvm-reset-package.aspx 

[karandeep963]

Hello All,

 

I have gone through both the Roman's link http://www.cadence.c...t-package.aspx  and  bhunter's paper http://www.synopsys....unter_paper.pdf.

 

I also find http://verificationhorizons.verificationacademy.com/volume-8_issue-2/articles/stream/on-the-fly-reset_vh-v8-i2.pdf mentor technique to use a response field in the seq_item and sequence and driver poll on the response. but in this i am unable to find what has been done with the sequences that are fired and waiting for finish_item(). Indeed it need a lot of changes in terms of addition of this response technique almost everywhere ,which would make the environment unstable i guess !!

 

What I found next is cadence is using its own library , while synopsys is preferring the reset phases which is unstable and may be depreciated soon(as per paper).

 

So unable to reach at any decision what can be followed.

 

I heard Cypress has published some paper anywhere and indeed they are able to use it perfectly , can any one get me to that paper so that I will carry my search forward.

 

It is also requested if anyone has any other better solution please let it be known.

 

Please correct if I am wrong with my understanding above.

 

Thanks,

Karandeep