nslmike Posted December 19, 2013 Report Share Posted December 19, 2013 Hello everybody. How to verify RTL's reset processing? It seems, there are no examples to demonstrate it. My RTL design is optimized with synchronuous reset, but resest signal do not feed all registers (for example no need to reset shiftregs in many cases, but resettig FSM is a must). I have already found some bugs in reset processing, but I want to do it with UVM. What is a way to do it? One more agent, including driver & monitor for reset? One more seq_item for it? Quote Link to comment Share on other sites More sharing options...
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