Scopes in systemc vcd files

[thomas.haber]

Usually simulator put a struture of scopes into the vcd file.

So in the viewer its much easier to get through the signals.

But SystemC does not by default.

Instead they have dots in the name.

 

$scope module SystemC $end

$var wire   32  aaa  top.irx_hsdpa_top.HSI_CLC_REG [31:0]  $end

.....

 

Is it possible to change systemCs mind ?

 

regards,

thomas

 

[kocha]

Hi, thomas

 

I using this script to new vcd file.

 

Manipulate the Hierarchy of VCDs generated by ASI (OSCI) PoC SystemC Simulator

http://thawedoutnow.blogspot.jp/2013/04/manipulate-hierarchy-of-vcds-generated.html

 

Regards,

kocha

[Philipp A Hartmann]

Kocha,

 

Manipulate the Hierarchy of VCDs generated by ASI (OSCI) PoC SystemC Simulator

http://thawedoutnow.blogspot.jp/2013/04/manipulate-hierarchy-of-vcds-generated.html

 

this looks like a nice utility and may be useful to the SystemC community in general.
Have you considered to upload/share this in the new SystemC community uploads area?

 

Greetings from Oldenburg,
  Philipp

[kocha]

Hi, Philipp

 

The owner of this script so @ytakatsukasa, it is not me.

I'll try to talk to him.

 

Regards,

kocha

[Guest ytakatsukasa]

Hi Philipp,

 

I wrote the program kocha introduced.

Thanks kocha for informing me.

 

The source code is available at github and it is licensed under GPL2.

I feel happy if the tool helps engineers, so I am OK to unploading it.

 

Should  uploaded data to SystemC community uploads be licensed under some specific license like that of PoC Simulator?

If so, I will consider making it dual-licensed.

 

Regards,

Yutetsu.

[Philipp A Hartmann]

Yutetsu,

 

thanks for considering to upload the tool to the SystemC community uploads.  I didn't check the licensing terms of the upload area before, but when you try to upload files there, you will be asked to confirm the following:

 

All material uploaded to the Accellera Community Uploads Area is licensed under the Apache License, Version 2.0 and may be publicly downloaded. By uploading material, you indicate your acceptance and compliance of the license.

 

As the Apache License less restrictive than the GPLv2 (but still GPLv2 compatible), it's up to you whether you want to your tool available under these terms.  Alternatively, you can eventually upload a short technical report, describing the functionaliy of the tool and add an external link to the GitHub repository.

 

Thanks,
  Philipp

[thomas.haber]

Hallo Kocha,

 

many thanks for the hint.

 

regards,

thomas

[ytakatsukasa]

Philipp,

 

Thanks for the license information.

I will face-lift the source code and upload it under Apache License.

 

thomas,

Sorry for wandering from the original topic.

I hope the PoC simulator emit VCD with the hierarchical structure,

and it seems technically possible with some patches to the PoC simulator.

I will think about it.

 

Regards,

Yutetsu.

[ytakatsukasa]

I wrote a patch to achieve this topic.

I only tested with examples/sysc/pkt_switch, but it emits like followings after add some sc_trace()'s in sc_main().

The patch is available at github.

 

 

$scope module SystemC $end
$scope module signal_0 $end
$var wire    1  aac  dest0       $end
$var wire    1  aad  dest1       $end
$var wire    1  aae  dest2       $end
$var wire    1  aaf  dest3       $end
$upscope $end
$scope module signal_1 $end
$var wire    1  aai  dest0       $end
$var wire    1  aaj  dest1       $end
$var wire    1  aak  dest2       $end
$var wire    1  aal  dest3       $end
$upscope $end
$scope module signal_2 $end
$var wire    1  aao  dest0       $end
$var wire    1  aap  dest1       $end
$var wire    1  aaq  dest2       $end
$var wire    1  aar  dest3       $end
$upscope $end
$scope module signal_3 $end
$var wire    1  aau  dest0       $end
$var wire    1  aav  dest1       $end
$var wire    1  aaw  dest2       $end
$var wire    1  aax  dest3       $end
$upscope $end
$scope module signal_4 $end
$var wire    1  aba  dest0       $end
$var wire    1  abb  dest1       $end
$var wire    1  abc  dest2       $end
$var wire    1  abd  dest3       $end
$upscope $end
$scope module signal_5 $end
$var wire    1  abg  dest0       $end
$var wire    1  abh  dest1       $end
$var wire    1  abi  dest2       $end
$var wire    1  abj  dest3       $end
$upscope $end
$scope module signal_6 $end
$var wire    1  abm  dest0       $end
$var wire    1  abn  dest1       $end
$var wire    1  abo  dest2       $end
$var wire    1  abp  dest3       $end
$upscope $end
$scope module signal_7 $end
$var wire    1  abs  dest0       $end
$var wire    1  abt  dest1       $end
$var wire    1  abu  dest2       $end
$var wire    1  abv  dest3       $end
$upscope $end
$upscope $end
$enddefinitions  $end

 

Regards,

Yutetsu.

[sumit_tuwien]

 Yutetsu,

 

I am confirming that this is working for other designs!

 

I think I can make the change for SystemC-AMS vcd file.

 

I recognize and would like to thank you for the contribution. World is good with people like you around.

 

Regards, Sumit

[ytakatsukasa]

Sumit,

 

I appreciate your feedback.

I found a big problem in the previous patch, only 1 bit wire is dumped.

Fixed version is uploaded to github.

The latest vesion checks environmental variable SC_VCD_NO_HIERARCHY and if it is set, behave as the original one.

 

Regards,

Yutetsu.