prads Posted May 19, 2010 Report Share Posted May 19, 2010 Hi All, I'm trying to convert an example from ovm2.0 to uvm1.0ea and getting the followingcompilation error: ** Error: ..alu_sequencer.svh(8): Failed to find name 'get_type' in specified scope. The above error is related to `uvm_update_sequence_lib_and_item() The Sequencer code is given below: class alu_sequencer extends uvm_sequencer #(alu_sequence_item, alu_sequence_item); `uvm_sequencer_utils(alu_sequencer) function new(string name = "", uvm_component parent = null); super.new(name, parent); `uvm_update_sequence_lib_and_item(alu_sequence_item) endfunction function void build(); super.build(); endfunction: build endclass: alu_sequencer Can someone please tell me what am I doing wrong here? Quote Link to comment Share on other sites More sharing options...
KathleenMeade Posted May 19, 2010 Report Share Posted May 19, 2010 (edited) Hello - I don't see anythng wrong in your sequencer code unless you have a typo? `uvm_update_sequence_lib_and_item(alu-sequence_ite SPACE m) I've included a very simple example that ran cleanly for me(ade) on IES9.2! //To RUN: % irun -incdir $UVM_HOME/src $UVM_HOME/src/uvm_pkg.sv seq_test.sv module seq_test; import uvm_pkg::*; `include "uvm_macros.svh" class alu_sequence_item extends uvm_sequence_item; rand logic [7:0] data; `uvm_object_utils_begin(alu_sequence_item) `uvm_field_int(data, UVM_DEFAULT) `uvm_object_utils_end function new(string name="alu_sequence_item"); super.new(name); endfunction : new endclass : alu_sequence_item class alu_sequencer extends uvm_sequencer #(alu_sequence_item, alu_sequence_item); `uvm_sequencer_utils(alu_sequencer) function new(string name="", uvm_component parent=null); super.new(name, parent); //`uvm_update_sequence_lib_and_item(alu_sequence_ite m) `uvm_update_sequence_lib_and_item( alu_sequence_item ) endfunction function void build(); super.build(); endfunction : build endclass : alu_sequencer endmodule : seq_test I hope this helps! Kathleen Meade Cadence Design Systems Edited May 19, 2010 by KathleenMeade Added signature information Quote Link to comment Share on other sites More sharing options...
adielkhan Posted May 20, 2010 Report Share Posted May 20, 2010 Kathleen's Testcase runs fine on VCS I checked with version VCS-2009.12-5. You can contact vcs_support@synopsys.com for VCS download instructions. CMD: vcs -sverilog $UVM_HOME/src/uvm_pkg.sv +incdir+$UVM_HOME/src seq_test.sv -timescale=1ns/1ns -R thanks, adiel@synopsys.com Quote Link to comment Share on other sites More sharing options...
prads Posted May 20, 2010 Author Report Share Posted May 20, 2010 Hi Kathleen and Adiel, Thanks for your time and effort, I was able to solve the issue. It was an issue with some file ordering in the package file. regards, Prads Quote Link to comment Share on other sites More sharing options...
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