Jump to content

Don't care bit handling in UVM RAL

Recommended Posts

Not sure do you have similar problem? I have a problem in handling the reset value in RAL.

f the reset value of a field in the register is don't care, what can I do for it?

Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked.

Do you guys think it is a feasible way? Thanks.

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...