Search the Community
Showing results for tags 'dont care'.
Found 1 result
Don't care bit handling in UVM RAL
kurtlin posted a topic in UVM SystemVerilog DiscussionsNot sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.