shekhar.iitm Posted May 28, 2013 Report Share Posted May 28, 2013 why do we have the base class as uvm_void in uvm library even though it doesn't have any variables or functions? what purpose does it serve? Quote Link to comment Share on other sites More sharing options...
dave_59 Posted May 28, 2013 Report Share Posted May 28, 2013 It serves no purpose other than legacy from OVM, and in the OVM it served as legacy from the URM/eRM. This class is the top of the class inheritance hierarchy. SystemVerilog has no need for a class that serves as a base of all classes, but Specman e did have this concept. Somebody though they would need to have a common root base class, so they added it to the library, but it turns out it is not needed in the UVM. Quote Link to comment Share on other sites More sharing options...
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