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why is uvm_void class need in uvm library

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It serves no purpose other than legacy from OVM, and in the OVM it served as legacy from the URM/eRM. This class is the top of the class inheritance hierarchy. SystemVerilog has no need for a class that serves as a base of all classes, but Specman e did have this concept. Somebody though they would need to have a common root base class, so they added it to the library, but it turns out it is not needed in the UVM.

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