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class invoke itself

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I saw a code like this:

class xxx_register extends uvm_component;


xxx_register m_root;

xxx_register m_parent;

xxx_register m_children[$];


I was confused by this. How can you define/use a class in itself as "xxx_register m_root/parent/children" in xxx_register? This seems not a static function. thanks.


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thanks dave. This presetation clarifies the structure and its function. I still have a question on it: how can you implement this structure in "true life"? You defined a class and in this class you use it, which seems a infinitive loop. Maybe they are in fact pointers? e.g. in my post before, I guess although m_root/parent/children is defined as class xxx_register instance, they are not an instance of xxx_register but a pointer to xxx_register. did I understand right? thanks

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Yes, m_root/parent/children are not instances of xxx_register, they are class variables that will contain handles that reference class instances of xxx_register. SystemVerilog does not have pointers like in C/C++. A pointer is an address that references a location in a uniform memory. A handle is an abstract concept that references a particular class instances. There is no way to see the value of a handle; you can only see what it references.

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