[Why don't we use smart pointer in systemc-2.3.x?]

Good point. I don't know that there are any plans currently. Probably needs to be suggested. Both unique_ptr and shared_ptr overloads would be good. 

You could of course extend the class and add your overload.

Caution: if used in bridges or adapters, there may be additional considerations. So you need to be careful to consider the expanded situation.

You may want to consider for what situations you wish to do this. Many use cases simply don't warrant smart pointers because the data is persistent or static.

 

[VCD Dump with Moving Time Window]

Nope; however, some EDA vendors have extended tracing and offer other faster formats for saving the traced data.

Hopefully, you are not debugging RTL, since that is better suited for SystemVerilog.

You can also speed up things by being very selective in what you trace (i.e., don't trace everything just because you can).

 

[I use tlm_extension to set/get trans extension, when does the memeory I new to delete?]

https://www.doulos.com/training/soc-design-and-verification/systemc-tlm-20/

[Why don't we use smart pointer in systemc-2.3.x?]

For many years, SystemC used C++98/03. The latest version of the standard (2023) moves to C++17. So I expect to see more smart pointers (esp. unique_ptr<T>).

There are certainly practitioners already using smart pointers in their code; however, example code usually constrained itself to the pre-C++11 standard.

I suggest using the make_unique<T>() and make_shared<T>() methods because they have some extra safety over using new.

Be careful to use the right type of smart pointer to avoid unnecessary overhead. I suggest you read the C++ Core Guidelines.

Important: You will need the SystemC library to be compiled for the C++ version you use. I suggest building the modern way with cmake.

[Running SystemC on new Apple M1 silicon]

You need to be sure you don't have any lingering x86_64 libraries (library files end in .a or .so)  lingering on your machine. I had to search out all my libraries and replace/upgrade them with the appropriate versions.

If you are using Qt, be sure it's compiled to arm64.

If you are using Homebrew or MacPorts, you will need to make sure they also compile to arm64.

[I use tlm_extension to set/get trans extension, when does the memeory I new to delete?]

This depends slightly on the coding style (Loosely timed (LT) vs Approximately Timed (AT)) and the extension classification. For AT, if you use the auto-extension mechanism, then the memory manager can do this for you. For sticky extensions, you don't remove the extension at all because it gets reused. For LT, it should be done in the component that creates the extension when the transaction is closing.

This is a relatively complex topic, which is covered in the Doulos TLM Adopter course, among other places.

[Note: I work as an instructor at Doulos.]

[sc_signal]

However, if you intend to provide an initial value before anyone reads the signal, that can be accomplished during start_of_simulation.

SystemC is designed with idea that hardware is fabricated (I.e., constructed or instantiated) and connected (aka port binding) before power is applied (i.e., active simulation starts). Formally, this is broken up into two major phases known as elaboration (i.e., construction and binding) and simulation. 

You can read about this in the standard (IEEE 1666-2023) sections 4.2 (elaboration) and 4.3 (simulation). You can obtain a free copy of the standard via a download at the end of https://systemc.org/overview/systemc/ .

If you are trying to simulate the idea of dynamic connections (e.g., plugging in/out a USB port or cell phones coming within range of a tower), you can accomplish that by fully connecting up all possible USB devices to a custom channel and then managing the state fo that channel (e.g., active or inactive).

[Can we use vector include simple_initiator_socket?]

Use sc_vector instead. See IEEE-1666 for details. 

[segmentation fault due to sc_signal<vctr*> B_in;]

To track down segment faults I recommend using gdb as follows:

% # Assume compiled executable is called run.x
% gdb run.x
gdb> break sc_main
gdb> run
... make sure you get here
gdb> continue
... crash happens
gdb> backtrace
... displays stack trace where crash occured.
... examine each frame looking for code you recognize as yours
... it will tell you the exact FILE_NAME and FILE_NAME where it went South
gdb> break FILE_NAME:FILE_NAME
gdb> run
... it will stop at the problem area
... you can examine the variables

Purchase and read the GDB manual. You will forever benefit from this.

[segmentation fault due to sc_signal<vctr*> B_in;]

For starters, an sc_signal on a pointer won't work very well since signals depend on comparing the values. Comparing pointers is likely to provide the right answer. You really need to wrap your data in a class and provide the required:

1. Default constructor
2. operator==
3. operator=
4. ostream operator<<

Please consider putting a small example of your source code on EDAplayground.com so that we can see and think about your issues more deeply.

[Getting blank output when running the program, Am i using topmodule correctly?]

What is fetchunit.h?

Can you put your code on edaplayground.com and share the link?

 

[Is the UVM write_* imp port function by default a static function?]

No but is all too common for newbies to no realize when pushing transactions through a port to forget to make a copy. Transactions in SystemVerilog are represented by classes, and transaction objects are referenced. Put and get do not copy by value.
 

[non-blocking transport interface of AT modeling]

@bsipl_h When modeling, you need to be asking yourself some fundamental questions:

1. Why are you modeling?

1. To determine the feasibility of a new architecture (interconnect)?
2. To understand timing issues?
3. To create a golden standard against which to RTL development?
4. To allow firmware development to start early?
5. To share with an external customer?
6. To use synthesis tools?

2. What is the focus of the model?

1. A single component
2. An entire system
3. Interoperability with another system
4. Post silicon validation

3. Who is your customer, and what do they need?

1. Architect
2. Verification team
3. Firmware team
4. Validation team

4. How "configurable" will the model be?

1. Limited
2. Allow different timing models/mixes
3. Support different teams
4. Support different connectivities

5. Are there simulation performance goals?

1. The more details you add, the slower the simulation
2. With fewer details, accuracy may be impacted
3. What is reasonable it required?

6. How much development time do you have for the model?

1. How much validation is needed?
2. How does it impact others' schedules?
3. How long do you expect this model to be used?
4. How much time do you have?
5. Can you acquire parts of the model from the teams or externally?
6. Can you purchase parts of the model?

Answers to the above questions will drive your decisions.

 

[Is there any way to initialize input port in module?The problem occurs in reset function when i initialize readdata32_16 port.]

One more hint: Try https:://www.EDAplayground.com when learning SystemC. It is easier to share your ideas/problems from there.

[Is there any way to initialize input port in module?The problem occurs in reset function when i initialize readdata32_16 port.]

There is a fundamental SystemC misunderstanding here. Ports do not store data nor do they have any associated "value". A port merely provides access to a channel and specifies which methods are available via the interface. The "value" to be initialized would be in the channel.

sc_in < sc_int<32>>readdata32_16;

The above specifies that readdata32_16 is connected to a sc_signal channel that manages sc_int<32> data. The port uses an sc_signal_in_if interface, which is restricted to using the read() access method. You may not write data via a sc_in port.

Also, you have fundamental misunderstandings about how time moves forward in SystemC. sc_start does not move time. You need to be using sc_core::wait().

Observation: Most of your code in sc_main() should be moved into a thread in a top-level module. Main should only be responsible for instantiating a single top-level module, starting the simulation, and performing clean-up at the end. Stimulus should be placed in a thread. Observation also needs its own SystemC process.

 

[setup of systemC]

Hopefully you are using the Cmake build process for your systeC library.

[Questions about SystemC simulation time]

How about transferring your code onto EDAplayground.com? You can then add statements to show time there. Then share the link.

 

[What is the difference between set_data_length() and set_streaming_width() in tlm_generic_payload]

Yes, that is what it is supposed to do.

[sc_signal cannot have more than one driver error]

Many writers detects race conditions.

[UVM-SC for HLS]

 

If used correctly, the design of UVM is such that the changes should be restricted to the DUT interface.

[Best way to pass parameters trough modules]

The discussed issue indicates a lack of proper understanding and mastery of C++ by the originators of this thread. Both @João Paulo and @songlin941111 need to obtain a better education in C++. There are many ways to do this, but it is fundamental to success with SystemC. SystemC is not C; although, I find many folks don't understand this. You can indeed understand a lot of SystemC with just a C background, but you truly do not understand SystemC until you fully understand C++.

C++ templates are a compile-time abstraction. As @Eyck and @maehne suggest, constructor arguments are the right way to go, which probably means using some base classes (e.g., sc_int_base or sc_uint_base -- see IEEE-1666-2011 section 7.5 and following) rather than templates. The use of CCI would also be appropriate to augment this.

 

 

[ofstream not working inside SC_CTHREAD]

Your problem is definitely not SystemC. You did not specify how it’s not working. I have some observations though:

1. f.close is not reachable due to the infiinite loop. 
2, you did not check for the success of opening the file.

[How to define `sc_fixed` variables that have word/integer lengths that are based off (but not the same size as!) those of a template parameter]

If not intended for direct synthesis (i.e., HLS), you could use the sc_fix and sc_ufix base classes. See IEEE-1666-2011 section 7.1 for more information. Section 7.10.7 describes the accessor methods to interrogate incoming objects. The non-"ed" classes simply use the constructor to establish the parameters.

It's all basic C++ stuff.

 

 

[Questions about SystemC simulation time]

First, the statement "systemc can't do system-level parallelism" is misleading and depends significantly on what you are trying to do. SystemC uses an event-driven simulation model in the same vein as VHDL and SystemVerilog. It can simulate parallism (concurrency) for both hardware and software, when correctly used.

Second, your description of what you are doing is not clear. Please provide:

1. a diagram illustrating module boundaries, processes, and FIFOs
2. provide your code (ideally on EDAplayground).

 

[Error: (E521) immediate notification is not allowed during update phase or elaboration phase]

Without code to look at, you won't likely get much help.