David Black

I suspect your problem is not understanding that the default action for SC_ERROR is to throw an exception. So you have two choices: 1. Surround calls with a try/catch block. 2. Change the default action to SC_DISPLAY without SC_THROW. I would also suggest you use the SC_REPORT_ERROR() macro so that you get the file and line number where the call originated.

Your problem is C++ rather than SystemC. "Initialization" should be titled "construction". You either need to use the initializer list to invoke the constructor, or if you are using C++11, you can use uniform initializer syntax.

This has nothing to do with SystemC, but more to do with your declaration. You are declaring an array of pointers to integers on the stack. Stack in SystemC is 64k by default, which means you are limited to 64k/sizeof(int*). I suspect you intended to declare a pointer to an array of ints: int (*matrix)[]; // Pointer to array of int or int** matrix; I suggest you read at least one of the following: https://www.codeproject.com/Articles/7042/How-to-interpret-complex-C-C-declarations https://www.geeksforgeeks.org/complicated-declarations-in-c/ https://medium.com/@bartobri/untangling-complex-c-declarations-9b6a0cf88c96 For simplicity, I like the following tool: https://cdecl.org

First thing you need to realize is that sc_signal<> is not a wire and it is not a data type. sc_signal<> is a channel with a non-blocking write and a blocking read. You cannot "connect" a variable to a signal. You have to explicitly make the transfer each time the value changes. There is no equivalent to a Verilog continuous assignment. How do you know if a signal has changed? You have to explicitly watch/wait for the change using additional methods value_changed_event() or possibly posedge_event() if using sc_signal<bool> or sc_signal<sc_logic>. Due to overloading of operator=(), the innocuous looking busCON10 = var_bus_CON[10] turns into: busCON10.write(var_bus_CON[10].read()); which will not return a value until the end of the next delta cycle. Using a cout << busCON directly after this will yield the current delta's value.

SystemC follows event driven simulation semantics to simplify hardware modeling. In part, this means using a cooperative multi-tasking model rather than a modern pre-emptive model. In this respect, SystemC is like SystemVerilog and VHDL. This makes it easier to focus on the modeling aspects rather than worrying about mutexes, volatility and other interactions due to multicore and parallel processes. Advanced SystemC users can use OS threads for some tasks, but the synchronization aspects are up to the programmer. So SC_THREAD's are not pre-emptive (nor are SC_METHOD processes) and hence a straightforward SystemC model is single core single threaded from an OS/software point of view. Additionally, you should be aware that the SystemC scheduler is not thread-safe for the most part. If you make use of async_request_update(), you can use multicore and parallel processes to interact with SystemC events. This assumes you are an expert programmer and proficient with C++ (not for beginners). There have been and are some efforts underway to standardize parallelization in SystemC, but it is a volunteer effort and you need to be on the SystemC LWG group to participate. Some commercial entities have developments underway, but keeping those closed for the time being. Always keep in mind that SystemC is not freeware, but was created as part of a commercial coalition to standardize modeling across/between companies. Don't think of SystemC as a free simulator. Also, SystemC is often mistaken as a competitor/alternative to SystemVerilog/VHDL, which it is NOT. SystemC was intended for high-level modeling and abstractions above RTL. The ability to co-simulate with RTL is a requirement for some of the use-cases. SystemC is used quietly by many large corporations to augment specification and verification. It differs from the other languages in that it uses an off-the-shelf C++ compiler and has no requirement of a specialized compiler. This benefits companies with huge software development teams using SystemC Virtual Platform models for early software development. The downside of this approach is the C++ compiler has no understanding of the SystemC domain and has no way to make optimizations that SystemVerilog/VHDL do (e.g. clocks). That is one reason that SystemC coders are advised to avoid explicit clock models to gain performance. Keep the design at as high a level of abstraction as you can.

sc_vector was designed for use during elaboration. sc_vector semantics are based on std::vector. For that matter, why are you not using std::vector? Are you passing an elaboration call. Furthermore, you would simply pass variables by reference in C++ anyhow. For a 2-dimensional array you would simply use a vector of vectors. Your basic problem sounds like a severe lack of C++ basics.

Q1: How are you declaring the processes? [Note: Seeing actual code would help a lot. Your descriptions are completely inadequate for anybody to understand exactly what you are asking.] Q2: What book are you using to get trained on using SystemC?

You should set length to sizeof(Array). Also, where are you locating the array? It should be static or allocated on the heap and not passed on the stack (e.g. automatic variables are located on the stack).

Use member data for the memory. Assuming your two modules are endian and floating point compatible, you can just do a normal TLM transfer using a simple cast to a character array. If your original array is float, then you need to use sizeof to get the proper depth. You did not note whether this is AT or LT, but that should not matter.

Don't use recursion? Remember that the stack size applies to each process (SC_THREAD and SC_METHOD), and the machine you are running on needs to have enough memory to accommodate this. If you have 16 threads running with 1G stack, then you need a machine with 16G just for your threads.

Yes, of course. An example would be modeling interrupts, which is often done with an sc_signal<bool>.

Java / C# interface is precisely what SystemC interface is. Your original question was more about port aggregation. The problem is that Verilog ports are really quite a different concept. To be sure , there are superficial similarities, SystemC is not an HDL. Mind you, it is quite easy to aggregate SystemC ports. Just define an aggregate class derived from sc_port. This would also allow you to crate aggregate methods (I.e. beyond simple bind). Just don’t expect this to be useable in synthesis. Perhaps a savvy EDA vendor will pickup on This if there is sufficient commercial interest, which I doubt.

Using new and malloc are supported for the verification side of SystemC. In other words, when you are creating a validation simulation.

SystemC is very well adopted already and has no need to provide free tools. Also, the purpose of Accellera is to develop standards for the EDA and engineering community, not free tools for academia. For this it has done quite well and continues to do an excellent job. Accellera is made up of volunteers from member companies and many of these do not get paid for their participation. In fact, there are very few that are paid staff for Accellera, and most of those are administrative only without the necessary skills to develop such tools. All contributions for Accellera are strictly volunteer and donations. More to the point, member companies develop and sell tools that do exactly what you are asking. So they have zero motivation to give away what they use to create income for themselves. So if you would like to develop such a tool on your own time and donate it, I am certain others would applaud your efforts; however, you should also not be surprized if your donation is rejected because it might hurt existing products of the member companies. If you would like to get a full time job with one of the member companies, do not be surprised to learn they expect you to have knowledge in SystemC to do some of the work you are hired for. Some companies might even send you to get trained. Finally, if you are interested in "free" tools that convert SystemC to Verilog, you might want to checkout Xilinx Corporation's VivadoHLS, which is as close to free as I think you will get for this type of very complex tool. It is restricted to developing code to be used inside Xilinx FPGA's and does a very decent job. You can also talk with other EDA companies about the possibility as a student of your university acquiring low cost versions of other commercial tools for use in graduate classes.

For synthesizable SystemC, there is a standard, but even so it is VERY vendor/software dependent. So the answers for using SystemC in a synthesizable context depend on which synthesis software you intend to use. Several companies often software for this (including, but no limited to, Cadence, Xilinx, Mentor (now Siemens)). In general, my experience is that most C/C++ is synthesizable subject to some simple restrictions (e.g. may not use the heap (i.e. new/delete/malloc/free), which also often means you will not be able to use very much of the STL, which is heavily dynamic. Polymorphism is restricted if not forbidden by most of the tools as well. That said, I have successfully synthesized huge designs fairly easily and with decent results.

Simple Bus is just a couple of custom channels with fairly simple API. Decode occurs in the bus fabric after interrogating the slaves about their individual address maps. Execution of transfers takes place in the context of respective master threads (initiators). The only other process used is an arbiter. We teach this bus in Fundamentals of SystemC course, which you can learn about here <https://www.doulos.com/content/training/SysC_training.php>. Of course, most folks just skip Simple Bus and go for an implementation based on TLM 2.0. For a Simple Bus application, Loosely Timed would be the appropriate abstraction.

Before you go passing arguments to processes in SystemC, I would ask you to be careful of the lifetimes of your variables if passed by reference. Also consider that you could also pass values as class (module) member data.

In general, SystemC models should avoid using clocks altogether. This is good for many reasons assuming your goal is high speed behavioral models. SystemC is often used for implementing functionally accurate virtual platforms that allow software to be designed well ahead of hardware delivery. Thus appropriate use of next_trigger() is actually a great idea. There is no way to distinguish between static and dynamic triggering at the point of invocation. Clock is synthesizable and if that particular mode of design is your goal, then sc_clock is appropriate. There are no features of SystemC itself that will tell you if the code itself is synthesizable. The answer to that is highly tool dependent. I know synthesis tools that require no clock at all, and others that insist a clock be specified. Always keep in mind: SystemC is simply C++ syntax used with a library and a methodology to model hardware and software. C++ has no concept of synthesizability. You have to go beyond GCC/LLVM to find out if your code is synthesizable with a given synthesis tool.

This question cannot be answered with respect to the SystemC standard as the issue is heavily implementation dependent. I am aware of implementations where SC_THREAD is faster than SC_METHOD and visa versa. It is also not a good basis for evaluating SystemC itself since the issue of simulation performance almost always comes down to how SystemC was used and how the modeler wrote their SystemC model. I do know an awful lot of folks use SystemC inappropriately (e.g. using it for modeling RTL, where VHDL or SystemVerilog are much better suited). IEEE 1666-2011 calls out the desired behavior, and not the implementation. Note: I did a presentation on SystemC myths many years ago at NASCUG that included the myth about whether or not one should favor SC_METHOD over SC_THREAD for performance reasons. It is quite simply a poor way of making a decision when attempting to obtain performance.

Study C++ (not C). If you learn C for this, you will get most things wrong and it will be much harder for you. C++ is not a small upgrade to C.

This is very basic SystemC. Assuming you will use an SC_THREAD, simply do a blocking read from the fifo and write to the appropriate address of the simple bus slave (peripheral). Suggest you take a class on SystemC or spend a lot of time reading up.

I concur with the idea of becoming more proficient in C++. This is the number one best way to improve your SystemC skills. It also helps to get good formal training on SystemC. Suggestions: Define your enum's inside your class declarations (e.g. inside a module). Then you enumeration items become CLASS_NAME::ENUM_NAME Adopt C++11 and use enum classes. See http://en.cppreference.com/w/cpp/language/enum for more details. Do both! Any serious C++ programmer should be using C++11 or C++14 by now unless restricted by some antiquated toolset. These are now well supported by modern versions of GCC, CLANG (LLVM), Microsoft Visual Studio, Oracle, and IBM. This even includes most embedded compilers.

I concur with Maehne's recommendations. Good SystemC requires mastering C++. If you can take a good class, it will accelerate your learning even more. Also, good C++ means throwing out much of your C habits and taking proper advantage of the easier (and safer) to code C++ STL containers and methods.

Are you doing this for your employer? Perhaps you need to look into getting formal SystemC training. I note that you did not answer the foundational questions I asked in my first response. Waiting...

Just to add a bit to Philipp's excellent reply: In part this was done to support EDA tools that support co-simulation of SystemC with other languages (e.g. SystemVerilog and VHDL). The EDA tools themselves implement main and then they can dynamically link in your sc_main as needed. Of course if you really know how to control the linker, there are other means as well, but we don't need to go there.