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Difference between Axi and TLM2.0
ARI posted a topic in SystemC TLM (Transaction-level Modeling)Hello Everyone, Could anyone please let me know what is the difference between Axi and TLM2.0. Which one is better, and where we can use both. Thanks
Getting a bit from bus
pmatheusvinhas posted a topic in SystemC LanguageHey. It's my first time with SystemC and I'm having the following problem: I made a control matrix that generates a 12 bits control word (sc_bv<12> CON) and I'm trying to get the 10th bit of that word. On my top level cpp I did the following: sc_signal<sc_bit<12> > bus_CON; sc_bv<12> var_bus_CON; var_bus_CON = bus_CON; sc_signal<bool> busCON10; busCON10 = var_bus_CON; and after I'm connecting the ref. variable that I want with that previous signal: programcounter.Ep( busCON10 ); And It's not working. My signal gives me hi impedance at all simulation time. A case that should happen when Ep = 0. p.s: matrix.CON( bus_CON ); Did I make anything wrong?
Consider the following code and the assertion to check for unknown data. If the code will change so that there will now be an array of valids and datas, what is the best way to change the assertion, so that for each valid, the corresponding data is checked.? Can I do it one line? (I had been considering using a generate statement around it.) module top; bit clk; logic write_valid; logic write_data; always clk = #5 !clk; initial begin clk=0; write_valid=0; #7; write_valid=1; #100; $finish; end as_showme : assert property (@(posedge clk) disable iff (!write_valid) (!$isunknown(write_data)) ) else begin $display("*** ERROR. write_data was unknown. ***"); end endmodule