chessat2002 Posted December 14, 2012 Report Posted December 14, 2012 Hi there, I'm facing a quiet annoying problem with my QuestaSim VHDL simulations. I'm using the following construct in my testbenches to terminate simulations: report "This is NOT an ERROR. This is the END of my simulation ..." severity failure; To start my simulation, I run a simple .do script like: run.do: ---------- ... run -all ... puts "We're done!" exit ---------- My problem is that the simulation "breaks" with the "failure" report statement and vsim is in the "paused" state afterwards. This means my macro (my run.do file) is "paused" at the "run -all" line and it won't execute the following statements. To continue the simulation (=execute the rest of the macro), I have to manually type "resume" in the GUI prompt. The desired behavior for me would be the following: In GUI mode: Run the full macro and ask if I really want tro exit simulation at the end. In batch mode: Run the full macro and terminate/exit at the end. I have already tried to find a solution using the "onfinish {...}" command but this didn't work. My QuestaSim version: 10.0d (revison 2011/12). Thank's a lot for your help! Alex' Quote
dave_59 Posted December 15, 2012 Report Posted December 15, 2012 VHDL 2008 added a package STD.ENV that contains stop and finish functions just like Verilog. This package can be used even if the VHDL is not compiled with -2008. http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_small/#env Quote
chessat2002 Posted December 15, 2012 Author Report Posted December 15, 2012 Hi dave, thanks a lot for your hint to this package. I'll have a look if it compiles with VHDL'87. However, I'm still sure that there must be any solution using parameters/variables. Thanks, Alex' Quote
dave_59 Posted December 15, 2012 Report Posted December 15, 2012 Do a search for "stop VHDL simulation modelsim" there is lots of information out there. Quote
ajeetha.cvc Posted December 16, 2012 Report Posted December 16, 2012 Have you tried: onbreak {resume} ? std.env.stop is the most modern way of doing this, but it will require beyond VHDL-1987. Ajeetha, CVC www.cvcblr.com/blog Quote
chessat2002 Posted December 20, 2012 Author Report Posted December 20, 2012 Hi! Thanks a lot, "onbreak {resume}" works fine! (I really don't remember the resons for discarding this idea ...) At the moment, I even have a second solution which just stops all stimuli generation to end simulation. Cheers, Alex' Quote
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