dakupoto Posted January 30, 2013 Report Share Posted January 30, 2013 Could some SystemC guru please provide some hints to my problem ? I am trying to translate some old VHDL code into SystemC, and running into issues. I have a VHDL entity with 3 input ports and one output ports. Of the 3 input ports, the data type of 2 is std_logic, which can be immediately translated to sc_dt::sc_logic. The other input port and the one output port has data type Boolesn. I am confused about how to convert VHDL statements that are executed always, into corresponding SystemC methods. If I use a SystemC SC_METHOD, they will always get executed, or alternatively use SC_THREAD and make the method sensitive to changes in the input ports. For example, if I have the following VHDL statement : rstall <= resetn and pcirst when PCIEN else resetn; (Here, 'resetn' and 'pcirst' are input ports of type std_logic in VHDL, and PCIEN is a Boolean environment variable) Any hint, suggestions would be of immense help. Thanks in advance for your help. Quote Link to comment Share on other sites More sharing options...
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