dwikle Posted November 28, 2012 Report Share Posted November 28, 2012 Hi, We have started using UVM-REG (coming from OVM-RGM) and I have run into an issue. The flow we use for writing registers in the DUT is to update each field value in the model, then execute the write. It seems that uvm_reg::update() is the proper way to do this, so our code looks something like this example: my_reg.a_field.set(1); my_reg.b_field.set(1); my_reg.update(status); What I have found is that if the register value is the same as in the model, the call to update() does NOT result in a transaction on the bus. I guess this is the desired behavior, since the documentation says this: "Write this register if the DUT register is out-of-date with the desired/mirrored value in the abstraction class, as determined by the uvm_reg::needs_update() method." My question is, is there a way to force the register to be written via the bus (frontdoor) even if the DUT register and the model register are the same value? This is the best that I came up with, but it seems clunky and I'm hoping there is a simpler way. I have to get() the current value of the model and send it to the bus using write(). my_reg.a_field.set(1); my_reg.b_field.set(1); my_reg.write(status, my_reg.get()); Thanks, Doug ps- Is there a way to format code on this forum? Seems bbcodes are turned off. Quote Link to comment Share on other sites More sharing options...
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