sandip.gaikwad Posted October 31, 2012 Report Share Posted October 31, 2012 Hello, In the RTL block that i am verifying there are register banks which are generated by using .rdl file. I am using the same .rdl files to generate the reg models using "reggen" and "ralgen" commands. This will give me multiple ral_block_<name> which extends uvm_reg_block. Can i directly use these multiple register models, like instantiating, creating them and the connecting in the tb_env? Or, do i need to make it as a single register model file i.e. a single ral_block_<name> class. Please guide. Thank you, Sandip Quote Link to comment Share on other sites More sharing options...
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