Can Multiple register models be used?

[sandip.gaikwad]

Hello,

In the RTL block that i am verifying there are register banks which are generated by using .rdl file. I am using the same .rdl files to generate the reg models using "reggen" and "ralgen" commands. This will give me multiple ral_block_<name> which extends uvm_reg_block.

Can i directly use these multiple register models, like instantiating, creating them and the connecting in the tb_env? Or, do i need to make it as a single register model file i.e. a single ral_block_<name> class.

Please guide.

Thank you,

Sandip

[petermonsson]

Hi Sandip,

You can have multiple register models in your environment. Often life is easier if you create a wrapper uvm_reg_block around the many generated blocks that you have.

Best Regards

Peter

[sandip.gaikwad]

Hey Peter,

I will try this out. Thank you!

regards,

Sandip

[janick]

If the use independent bus interfaces, they can be kept separate.

if they all use the same interface, they have to be contained in a higher-level block.