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sylvainb

What is the proper way to design coverage within a monitor?

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Coverage should sit along with protocol checkers within a UVC states the UVM user guide.

In SystemVerilog, it is achieved using covergroup within the monitor, these covergroups are built within the monitor constructor using the 'new()' method - At least it's what is done within the UVC we purchased from a vIP vendor. As a consequence, if I want to make a new derived class for the UVC monitor I am reusing in order to tailor the verification environment to the special needs of my DUT, I am not able to override the initial covergroup within the monitor base class...

Is there a better way to proceed? What is there the best practice for extending/modifying and existing covergroup?

Regards

Sylvain

Edited by sylvainb

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Hi,

In my opinion it is easiest to use a uvm_subscriber which is connected to the analysis port of the monitor. SystemVerilog has lots of limitations when it comes to inheritance and covergroups. You can have a look at an example of a coverage subscriber in cov_test_lib.sv in "Linear PCM integrated example test bench" in the UVM Contributions section.

Best Regards

Peter

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Hi Peter,

Thank you for you answer. I had indeed a look within the "Linear PCM integrated example test bench". I think the idea of separating the UVC monitor and the coverage by encapsulating the coverage groups within a uvm_subscriber is neat, however I can foresee that the example of the coverage library (lpcm_cov_lib.sv), using only the size as a parameter (16,24 & 32bits), can become easily extremely verbose and clumsy when the numbers of parameters increase and the parameters interact with one another to determine how the cover group should look like.

The best of course, would be to have a covergroup in the base class that can be extended and tweaked in a derived class, but I understand that this is not possible due to SystemVerilog language limitations...

Regards

Sylvain

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Hi Sylvain,

My functional coverage skills aren't that great. Covergroups can give you some flexibility which I haven't used in the example test bench. See for example section 20.4 in the SystemVerilog 3.1a standard. Maybe you can make something work.

Best Regards

Peter

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