arno Posted October 11, 2012 Report Share Posted October 11, 2012 The new uvm-1.1c changed the timeout to be fatal rather than error. But ithis change has introduced the following issue : the final phases are no longer executed at the end of the simulation. By instance, I have a timeout, I need the check phase to run to tell what is causing it. With uvm-1.1c., it is no longer possible. I think this is a problem that should be fixed : end of sim phases should be run in any case, timeout or not. Quote Link to comment Share on other sites More sharing options...
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