How to constraint bits of sequence item in sequence

[qwerty]

Hi,

I want to constraint the individual bits of address in my sequences.My address is of 44 bits. I want to generate random values for bits aaddr[20:10] and assign values to some bits aaddr[30]=1

Whats the best and the simplest way to do it. I tried some ways as shown below but it didn't work put

class  ud extends ud_base_seq;

  logic [43:0] prev_aaddr;

  rand bit [9:0]addres;
  constraint addr{addres > 19; addres < 24;}

  virtual task body();

for(int i=0; i<3; i++) begin
`uvm_do_with(req,{req.aaddr == {req.aaddr[20:10] inside{19,24}}

//`uvm_do_with(req,{req.aaddr == {1'b1, 2'd0, 3'b001, 3'd0, 4'd0, addres, 3'd0}
        prev_aaddr = req.aaddr;
        `uvm_do_with(req,{req.aaddr == prev_aaddr;})
   end
  endtask : body

endclass 

[maheshwarnk]

I am not sure but below line may creat problem:

`uvm_do_with(req,{req.aaddr == {req.aaddr[20:10] inside{19,24}}

give a try on :

`uvm_do_with(req,{aaddr[20:10] inside{19,24}

[whiteriver]

the syntax here is wrong:

`uvm_do_with(req,{req.aaddr == {req.aaddr[20:10] inside{19,24}}; )

it should be:

`uvm_do_with(req, { req.aaddr[20:10] inside {[19,24]}; } )

although I am not sure if it's allowed to do part-selection.

the other line also has a syntax error:

`uvm_do_with(req,{req.aaddr == {1'b1, 2'd0, 3'b001, 3'd0, 4'd0, addres, 3'd0}; )

should be:

`uvm_do_with(req,{req.aaddr == {1'b1, 2'd0, 3'b001, 3'd0, 4'd0, addres, 3'd0;})

you can also create more constraints in your addres, then randomize() it and send it to the sequencer (`uvm_do_with(req,{req.aaddr == addres;}))

[qwerty]

Hi guys, thanks for the reply. But its not working. I think part select is not allowed.

[dave_59]

When you say it doesn'tt work, what is wrong? Compiler error? Randomize fails?, or you are not getting results you expect?

I hope you realize this oddity of the SV LRM: when searching for identifiers in constraints, the object being randomized is searched first, then the local scope.

It looks like you named your identifiers differently in the sequence and seq_item, but you did not show the req item definition. But when you write your constraints like

`uvm_do_with(req,{req.aaddr == prev_aaddr;})

There is no need to write req.aaddr. just aaddr will work. if req also has a prev_aaddr member, it will use that first. If you want to force the prev_aaddr in the ud class. you should write the constraint as

`uvm_do_with(req,{aaddr == local::prev_aaddr;})