Trouble storing the interface handle into the uvm_object_db from the top module

[cliffc]

Subject: Trouble storing the interface handle into the uvm_object_db from the top module

Hi, All -

I must be doing something really simple wrong while trying to store the interface handle into the uvm_object_db.

I am using Questasim 10.1a.

The test files can be downloaded from the web page:

www.sunburst-design.com/UVM_OBJECT_DB

The uvm.f command file requires that the $UVM_HOME variables be set to the installtion of the uvm libraries on your computer.

You can see the error when you run: ./do_questa

The error message is:

# ** Error: (vsim-3978) top.sv(31): Illegal assignment to type 'virtual duf_if' from type 'interface dut_if': Vir. 'duf_if' interface must be assigned a matching interface or virtual interface.

If you comment out line 31 of the code, the test runs and prints the simple message.

The top-module code (available on the web site) is:

//----------------------------------------------------------------------

// This File: top.sv

//

// Copyright 2009-2012 Sunburst Design, Inc.

//

// Sunburst Design (Beaverton, OR):

// cliffc@sunburst-design.com

// www.sunburst-design.com

//----------------------------------------------------------------------

`timescale 1ns/1ns

module top;

import uvm_pkg::*; // import uvm base classes

import tb_pkg::*; // import testbench classes

logic clk;

// Instantiate clkgen

clkgen ck (clk);

// Instantiate DUT

// DUT must connect to internal interface signals hierarchically

pcnt i1 (.dout(dif.dout), .din(dif.din),

.ld(dif.ld), .inc(dif.inc),

.clk(clk), .rst_n(dif.rst_n));

// instantiate real DUT interface

dut_if dif (clk);

initial begin

uvm_config_db#(virtual duf_if)::set(null, "*", "vif", dif);

run_test();

end

endmodule

// # ** Error: (vsim-3978) top.sv(31): Illegal assignment to type 'virtual duf_if' from type 'interface dut_if':

// Vir. 'duf_if' interface must be assigned a matching interface or virtual interface.

Any hints would be appreciated.

Cliff Cummings

Verilog & SystemVerilog Guru

[mea1201]

Hi Cliff,

It was a misspelling. Your config DB set is typed with virtual duf_if. It should be virtual dut_if. At least that should get you past that error.

[cliffc]

Well I am completely embarrassed! Thanks, for spotting the error. I had looked at that code for hours and my eyes told me that all of the code referenced dut_if instead of duf_if. Looking at the error message now I can see the error very plainly!

Regards - Cliff Cummings

Maybe-not-so Verilog & SystemVerilog Guru!!