Roman Posted July 10, 2012 Report Share Posted July 10, 2012 In some IPs. there are many different width of registers with the same interface. For example(Read Operation): byte, word registers inside the IP , using the 32bits interface to access . 4 byte's registers will be packed in one word in the design. It always read the word from DUT. When we do the byte_en in reg2bus of uvm_reg_adapter, we met one issue. If the rw.addr[1:0] is 2'h0 , it's difficult to distinguish what's the width of the register which is accessed currently. Byte or Word register ? we could not assign the correct byte_en. if the register is byte width. we need to enable the Least Significant byte. and then compare the read data with mirrored data in reg model. So if there is width in uvm_reg_bus_op, it will be easy to handle for byte_en for each register access in reg2bus function. Quote Link to comment Share on other sites More sharing options...
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