[UVM REG] Why not add the size in the uvm_reg_bus_op's variables?

[Roman]

In some IPs. there are many different width of registers with the same interface.

For example(Read Operation):

byte, word registers inside the IP , using the 32bits interface to access .

4 byte's registers will be packed in one word in the design. It always read the word from DUT.

When we do the byte_en in reg2bus of uvm_reg_adapter, we met one issue.

If the rw.addr[1:0] is 2'h0 , it's difficult to distinguish what's the width of the register which is accessed currently. Byte or Word register ? we could not assign the correct byte_en.

if the register is byte width. we need to enable the Least Significant byte. and then compare the read data with mirrored data in reg model.

So if there is width in uvm_reg_bus_op, it will be easy to handle for byte_en for each register access in reg2bus function.

[janick]

Use the 'element' handle and get the number of bits in the register using the get_n_bytes() method.

[Roman]

Yes, get_n_bytes() method could work for this case.

But there is no 'element' handle in the reg2bus? how to make it happen?

For example

virtual function uvm_sequence_item reg2bus(uvm_reg_bus_op rw);

apb_item apb = apb_item::type_id::create("apb_item");

apb.op = (rw.kind == UVM_READ) ? apb::READ : apb::WRITE;

apb.addr = rw.addr;

apb.data = rw.data;

return apb;

endfunctio

[janick]

Use uvm_reg_bus_op::n_bits

[Roman]

Ok, I miss this item. Thanks Janick