fayz Posted March 25 Report Share Posted March 25 The problem occurs when connecting the ports in SOC module(TOP module), am i making a mistake?: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_6' (sc_in) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235 here is the link of the code: https://www.edaplayground.com/x/JfnT I want to achieve something like this shown in below picture. Quote Link to comment Share on other sites More sharing options...
AmeyaVS Posted March 25 Report Share Posted March 25 Hello @fayz, It seems you are trying to bind the following interface on: rv_thunder.d_dmem_out twice once within the rv_thunder module, and once on the SoC module level. This would not work. You possibly start by commenting the line no.: 84 in the design.cpp on the URL you have shared. Plus I would recommend going through the examples directory available with SystemC source/installation package to get a better idea, on using the library for modelling. Regards, Ameya Vikram Singh Quote Link to comment Share on other sites More sharing options...
fayz Posted March 25 Author Report Share Posted March 25 hey @AmeyaVS, If commented line 83,84 and 23,24 i.e input ports of rv-thunder module and their respective port binding in SOC module line 23 and 24 , now i get error related to output port: Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out) In file: D:\Download Data\new download\systemc-2.3.4\systemc-2.3.4\src\sysc\communication\sc_port.cpp:235 Quote Link to comment Share on other sites More sharing options...
Eyck Posted March 26 Report Share Posted March 26 You still have the same issue. If you would name your port this would help in debugging since the error message points to the respective port by name. A guess is that you bind the port readsig in the module control to a signal and d_memreadsig of module thunder in the SOC. It is a guess as all the other files are missing on edaplayground You need to keep in mind: a sc_port and hence a sc_in/sc_ouz/sc_inout only forward the functions of a signal. Therefore it can only be bound to a single signal, usually at top level. Another thought: it might be beneficial to write testbenches and unit tests for your leaf modules and then combine them up then you stumble upon sucher errors early on and based on your last increment. This makes it easier and helps you to understand the constraints imposed by C++ and SystemC. Quote Link to comment Share on other sites More sharing options...
fayz Posted March 26 Author Report Share Posted March 26 I have commented some ports in both SOC and rv-thunder module due to which i think error occurs, plus i had verified the rv-thunder module through testbench,which is working fine, here is updated version of code: https://www.edaplayground.com/x/QQcs Moreover, do you know any way to name these ports, so that it would be easy for debugging i.e Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'TOP.thunder_inst.port_4' (sc_out) Quote Link to comment Share on other sites More sharing options...
AmeyaVS Posted March 26 Report Share Posted March 26 Hello @fayz, For your query: 3 hours ago, fayz said: Moreover, do you know any way to name these ports, so that it would be easy for debugging i.e I would start by naming all the systemc objects: For e.g.: SC_MODULE(rv_thunder) { sc_out<sc_int<32>> add{"add"}; sc_out<sc_int<32>> d_dmem_data{"d_dmem_data"}; sc_out<sc_uint<1>> d_memwrite{"d_memwrite"}, d_memread{"d_memread"}; sc_out<sc_uint<2>> doutdmem_mask{"doutdmem_mask"}; ..... Hope this helps. Regards, Ameya Vikram Singh fayz 1 Quote Link to comment Share on other sites More sharing options...
David Black Posted March 27 Report Share Posted March 27 For slightly less typing and better consistency, I suggest using SC_NAMED macro, which was officially introduced in IEEE-1666-2023. It works under SystemC 2.3.3 and newer. Also, for better performance, unless you are synthesizing, I suggest using int32_t instead of sc_int<32>, and bool instead of sc_uint<1>. Anyhow, here is another take on naming ports, modules, and signals: SC_MODULE(rv_thunder) { sc_out<sc_int<32>> SC_NAMED(add); sc_out<sc_int<32>> SC_NAMED(d_dmem_data); sc_out<sc_uint<1>> SC_NAMED(d_memwrite); sc_out<sc_uint<1>> SC_NAMED(d_memread); sc_out<sc_uint<2>> SC_NAMED(doutdmem_mask); //... // Can do the same with modules and signals: Some_module SC_NAMED(other); sc_signal<bool> SC_NAMED(status); The macro SC_NAMED simply translates SC_NAMED(abc) into abc{"abc"}. Quote Link to comment Share on other sites More sharing options...
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