[virtual interface] Is is possible to pass one signal by task argument ?

[light12]

Below (Example 1) shows that success of argument passing for whole virtual interface signals.

But (Example 2) cannot work that I intended.

I want to pass only one signal of virtual interface to certain task.

Is it possible or not?

Could you explain why ?

Thanks in advance …

------------------------------------------------------------------------------------------

interface aaa (input logic clk_a1, input logic clk_a2);

endinterface

(Example 1)

class private_sb extends uvm_scoreboard;

virtual interface aaa aaa_vif;

virtual task run ();

check_dut (aaa_vif);

endtask

virtual task check_dut (virtual interface aaa aaa_vif_dut)

repeat (10) @(posedge vif_dut.clk_a1)

endtask

endclass

(Example 2)

class private_sb extends uvm_scoreboard;

virtual interface aaa aaa_vif;

virtual task run ();

check_dut (aaa_vif.clk_a1.);

endtask

virtual task check_dut (logic aaa_logic_clk)

repeat (10) @(posedge aaa_logic_clk)

endtask

endclass

[dave_59]

The problem is that by default, task arguments are copied by value when you enter the task, and that argument is a local variable to the task. You should change your task argument to a ref.

virtual task check_dut (ref logic aaa_logic_clk)
        repeat (10) @(posedge aaa_logic_clk)
   endtask

Then the code inside the task will see value changes from the variable outside the task.

The reason that your example 1) works is because the value of a virtual interface variable is a handle, which is already a reference to an interface instance. So copying the handle value in a local virtual interface variable still points to the same interface instance.

[light12]

Dear dave_59,

Thank you for your kine response.

But, compilation error is occurred after modifying codes.

I modified codes below following your guide.

Compile error(exactly, elaboration error) is that

"invalid ref argument usage because actual argument is not a variable"

Is it not possible to use "ref" argument on interface signal which is connected to DUT?

Thanks in advance..

(Example 2)

interface aaa (input logic clk_a1, input logic clk_a2);
endinterface

class private_sb extends uvm_scoreboard;
  virtual interface aaa aaa_vif;

  virtual task run ();
    check_dut ([B]aaa_vif.clk_a1[/B]);  [U][B]// compiler points that this line has error[/B][/U]
  endtask

  virtual task check_dut ([B]ref[/B] logic aaa_logic_clk) // (old) virtual task check_dut (logic aaa_logic_clk)
    repeat (10) @(posedge aaa_logic_clk)
  endtask
endclass 

[dave_59]

You will have to show the complete error message. It's possible the version of the tool you are using has a problem. It works for me in Questa.