How to share data(a vector) between two modules who can read and write

[Prepo]

I know that sc_fifo allows for one way communication from one module to another. We can also use sc_signal. But I am essentially trying to create a vector of data (like a shared memory) that can be read and written by multiple modules.I can just declare it as a global but looking for some other way so that I can write modular code for testing. Ideally I just want a sc_signal<std:vector<T>> data. But i think that is not supported. Is the option to inherit own class and implement? I just don't want to overlook some inbuilt systemc construct . Isn't it a common requirement?

[Eyck]

You might use sc_signal<std:vector<T>>

sc_vector<sc_signal<T>>

 

[Prepo]

Sorry, I thought sc_signal<std::vector<T>> was not supported. I cannot compile it so maybe in newer version? Also sc_vector unfortunately is not suitable for  as my vector is changing in size and dynamic binding will be an issue correct?

[David Black]

On 3/3/2023 at 11:27 PM, Prepo said:

Sorry, I thought sc_signal<std::vector<T>> was not supported. I cannot compile it so maybe in newer version? Also sc_vector unfortunately is not suitable for  as my vector is changing in size and dynamic binding will be an issue correct?

@Eycksuggestion was sc_core::sc_vector<sc_signal<T>>, there's no std::vector in there and the order is reversed. SystemC objects have special construction requirements that std::vector does not meet. His solution is clean.

Alternately, you could probably specify std::vector's allocator, but that would be much messier. See https://en.cppreference.com/w/cpp/container/vector/vector for details on this approach.

 

Or develop a simple Vector_channel with a simple API (i.e., sc_interface) with methods similar to std::vector<T>. But this too would be slightly messy compared to @Eyck's solution.

[Prepo]

Thank you