Error loading design during QuestaSim simulation of VHDL Design with SystemVerilog TB

[pratyaksharn]

Hello,

I am trying to create a UVM testbench on a VHDL Design.

I have created a make file to simulate the design with UVM testbench.

I am using Questasim 10.1 for the simulations.

The make file looks like this

"

vlib work

vcom -93 -f compile_source.f

vlog -f compile_tb.f

vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top

"

When I run the command , I am able to compile VHDL, SystemVerilog Code.

However I get the following error during elaboration.

"

Top level modules:

badge_tb_top

/tools/mentor/questa_sim_10.1/questa_sim/linux/vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top

Reading /tools/mentor/questa_sim_10.1/questa_sim/tcl/vsim/pref.tcl

# 10.1

# vsim +UVM_TESTNAME=rcc_base_test -c rccgpu badge_tb_top

# ** Note: (vsim-3812) Design is being optimized...

# // Questa Sim

# // Version 10.1 linux Dec 5 2011

# //

# // Copyright 1991-2011 Mentor Graphics Corporation

# // All Rights Reserved.

# //

# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS

# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.

# //

# Loading std.standard

# Loading std.textio(body)

# Loading ieee.std_logic_1164(body)

# Loading ieee.std_logic_arith(body)

# Loading ieee.std_logic_unsigned(body)

# Loading work.badgefuncpkg(body)

# Loading work.badgepkg

# Loading ieee.numeric_std(body)

# Loading work.rccgpu(rtl)#1

# Loading sv_std.std

# Loading mtiUvm.uvm_pkg

# Loading work.mem_if_sv_unit(fast)

# Loading work.badge_tb_top(fast)

# Loading mtiUvm.questa_uvm_pkg(fast)

# ** Error: (vsim-3171) Could not find machine code for '/home/prra/trunk/badgeComponent/testbench/uvm_tb_rccgpu/work.rccgpu(rtl)'.

# Error loading design

Error loading design

make: *** [questa] Error 12

"

I have also created a wrapper file in SystemVerilog and instantiated the wrapper in the top testbench file.

Please help.

[aji.cvc]

You are better off asking support@model.com for this. But as a blind guess, try using -novopt switch during vsim - just to isolate if this is due to some optimization issues. However remember to remove it in production run as it can have big impact on regressions.

Ajeetha, CVC

www.cvcblr.com/blog

[pratyaksharn]

Hello Ajeetha,

Thank you so much for your reply!!

I had created a wrapper around the DUT instance.

I was able to eliminate this error after removing the wrapper .. Strange but it worked!!

Thanks,

Pratyaksha