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pratyaksharn

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About pratyaksharn

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  1. Hello, Scenario 1. I have two UVCs driving the DUT. host and top 2. I am using virtual sequence to run the sequences of host and top 3. I have created a host_seq_lib of type host_sequence_library. 4. I want to randomly execute any of the sequences from the sequence library until a signal rises. Problem : I try to run host_seq_lib in my virtual sequence like this. class rcc_full_flag_seq extends uvm_sequence; // provide the implementations of virtual methods like get_type() `uvm_object_utils(rcc_full_flag_seq) `uvm_declare_p_sequencer(badge_vsequencer) // top de-assert reset s
  2. Hello Ajeetha, Thank you so much for your reply!! I had created a wrapper around the DUT instance. I was able to eliminate this error after removing the wrapper .. Strange but it worked!! Thanks, Pratyaksha
  3. Hello, I am trying to create a UVM testbench on a VHDL Design. I have created a make file to simulate the design with UVM testbench. I am using Questasim 10.1 for the simulations. The make file looks like this " vlib work vcom -93 -f compile_source.f vlog -f compile_tb.f vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top " When I run the command , I am able to compile VHDL, SystemVerilog Code. However I get the following error during elaboration. " Top level modules: badge_tb_top /tools/mentor/questa_sim_10.1/questa_sim/linux/vsim -c +UVM_TEST
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