Hello,
I am trying to create a UVM testbench on a VHDL Design.
I have created a make file to simulate the design with UVM testbench.
I am using Questasim 10.1 for the simulations.
The make file looks like this
"
vlib work
vcom -93 -f compile_source.f
vlog -f compile_tb.f
vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top
"
When I run the command , I am able to compile VHDL, SystemVerilog Code.
However I get the following error during elaboration.
"
Top level modules:
badge_tb_top
/tools/mentor/questa_sim_10.1/questa_sim/linux/vsim -c +UVM_TEST