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pratyaksharn

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About pratyaksharn

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  1. Hello, Scenario 1. I have two UVCs driving the DUT. host and top 2. I am using virtual sequence to run the sequences of host and top 3. I have created a host_seq_lib of type host_sequence_library. 4. I want to randomly execute any of the sequences from the sequence library until a signal rises. Problem : I try to run host_seq_lib in my virtual sequence like this. class rcc_full_flag_seq extends uvm_sequence; // provide the implementations of virtual methods like get_type() `uvm_object_utils(rcc_full_flag_seq) `uvm_declare_p_sequencer(badge_vsequencer) // top de-assert reset sequence top_ctrl_disable_reset_seq top_disable_reset; top_ctrl_enable_reset_seq top_enable_reset; host_seq_lib host_seqs; host_config cfg; // new constructor function new(string name="rcc_full_flag_seq"); super.new(name); endfunction : new virtual task pre_body(); // Get the configuration object if(!uvm_config_db #(host_config)::get(null, get_full_name(), "host", host_cfg)) begin `uvm_error("HOST_CFG", "host_config not found"); end host_seqs.selection_mode = UVM_SEQ_LIB_RANDC; host_seqs.min_random_count = 15; host_seqs.max_random_count = 30; endtask virtual task body(); `uvm_do_on(top_disable_reset, p_sequencer.top_ctrl_seqr) fork repeat(30); begin `uvm_do_on(host_seqs, p_sequencer.host_seqr) end host_cfg.wait_for_full_rise(); join_any endtask endclass HOwever I get an error * Fatal: (vsim-131) /home/prra/trunk/badgeComponent/uvm_testbench/rccgpu_tb/tb/badge_virtual_seqs.sv(53): Null instance encountered when dereferencing '/badge_tb_top/rcc_full_flag_seq::pre_body/this*.host_seqs Question - Can I run a sequence library inside a virtual_sequence?
  2. Hello Ajeetha, Thank you so much for your reply!! I had created a wrapper around the DUT instance. I was able to eliminate this error after removing the wrapper .. Strange but it worked!! Thanks, Pratyaksha
  3. Hello, I am trying to create a UVM testbench on a VHDL Design. I have created a make file to simulate the design with UVM testbench. I am using Questasim 10.1 for the simulations. The make file looks like this " vlib work vcom -93 -f compile_source.f vlog -f compile_tb.f vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top " When I run the command , I am able to compile VHDL, SystemVerilog Code. However I get the following error during elaboration. " Top level modules: badge_tb_top /tools/mentor/questa_sim_10.1/questa_sim/linux/vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top Reading /tools/mentor/questa_sim_10.1/questa_sim/tcl/vsim/pref.tcl # 10.1 # vsim +UVM_TESTNAME=rcc_base_test -c rccgpu badge_tb_top # ** Note: (vsim-3812) Design is being optimized... # // Questa Sim # // Version 10.1 linux Dec 5 2011 # // # // Copyright 1991-2011 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_unsigned(body) # Loading work.badgefuncpkg(body) # Loading work.badgepkg # Loading ieee.numeric_std(body) # Loading work.rccgpu(rtl)#1 # Loading sv_std.std # Loading mtiUvm.uvm_pkg # Loading work.mem_if_sv_unit(fast) # Loading work.badge_tb_top(fast) # Loading mtiUvm.questa_uvm_pkg(fast) # ** Error: (vsim-3171) Could not find machine code for '/home/prra/trunk/badgeComponent/testbench/uvm_tb_rccgpu/work.rccgpu(rtl)'. # Error loading design Error loading design make: *** [questa] Error 12 " I have also created a wrapper file in SystemVerilog and instantiated the wrapper in the top testbench file. Please help.
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