Cycle accurate TLM Models

[ManikantaAllam]

Dear Seniors,

 

I am new to SystemC. I come from VHDL Background. As part of my master's thesis, I am going to use the Cycle Accurate TLM modelling methodology. 

Though I have gone through various examples I am quite not able to get the sense of Cycle Accurate TLM models.  

Could anyone lead me to a library of examples (Could be a textbook/git library/ anything) that can be simulated and understood for the above-mentioned use case? or even briefly explain with a simple baseline example?

 

Thank you & Best regards

Manikanta

[David Black]

I won't show you a library, but I have one comment:

SystemC with TLM, in general, is generally used to model cycle "approximate", which is the basis for the Approximately-Timed modeling style described in the standards document. Virtual platforms and behavioral models tend to favor the less detailed Loosely-Timed modeling style for reasons of performance. If you model at the cycle "accurate"  level, then I don't see why you don't just go for RTL modeling since the overhead of cycle accuracy will tend to slow down the model to the same level.

Cycle-Approximate simply means that transactions take place with a roughly equivalent timing for transactions, but there are no events for each clock edge. In fact, efficient and fast models do not have any sc_clocks at all. They can still be very close in timing results but eliminate the incessant context switches imposed by real clocks (not to mention that half of the context switches are not even useful.

[ManikantaAllam]

Thank you so much Mr. David. 

 

Most of the literature regarding SoC communication modelling ( Buses/NoCs) termed as 'cycle accurate TLM simulations'. So I just wanted to get the clarity over this. 

 

Best Regards

Manikanta