Jump to content

Search the Community

Showing results for tags 'tlm2.0'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • SystemRDL
    • SystemRDL Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 5 results

  1. Dear Seniors, I am new to SystemC. I come from VHDL Background. As part of my master's thesis, I am going to use the Cycle Accurate TLM modelling methodology. Though I have gone through various examples I am quite not able to get the sense of Cycle Accurate TLM models. Could anyone lead me to a library of examples (Could be a textbook/git library/ anything) that can be simulated and understood for the above-mentioned use case? or even briefly explain with a simple baseline example? Thank you & Best regards Manikanta
  2. Hi, I am learning systemc/TLM2.0, I have a confusions in using the phases, When it comes to AT modeling, BEGIN_REQ and END_REQ are used to write data from initiator to target and BEGIN_RESP and END_RESP are use to read from traget to initiator OR we should split the write to target in 4 different phases and read from target in 4 different phases? I am aware of return path and early completion , i just want to have clearity on usage of request and response phases,
  3. Hello There is an existing model with tlm1.0 sockets - sc_port and sc_export. Is it possible to bind these sockets to tlm2.0 initiator and target sockets? If yes, then what is the conversion procedure involved? I'm new to SystemC, any help/insight on this is appreciated. Thanks.
  4. Hello, It is my first participation. I'm a master computer sciences student. I had program a code with SystemC 2.3.1 (includes TLM). I have some questions. Does SystemC 2.3.1 (includes TLM) includes TLM 1.0 ? What is the benefits of TLM 1.0? Can i use GTKWave with TLM 1.0 or it works just with SystemC RTL? What is the difference between TLM 1.0 and TLM 2.0 ? I would like to more understand TLM 1.0 any documents suggestions? Any help? Thanks.
  5. I am looking at MultiSocketSimpleSwitchAT example, and I can't seem to figure out how to implement priority based request selection. For example, in this simple switch, if we get multiple request on a given time, I need a stage where after collecting all the requests I can arbitrate between request in Round Robin manner. In this example, it is just selecting first request that happens to execute. Any suggestion on how can I implement that. Thanks
×
×
  • Create New...