Jump to content

does UVM support post-simulation after P&R


Recommended Posts

Hi,

until now I see lots of discussions on UVM for pre-simulation, which is without timing information extracted from backend. Is there any possibility that UVM supports post-simulation with timing information extracted after P&R? I guess it should because UVM is still systemverilog, but is there any detailed discusstion on it?

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...