chenyong Posted May 2, 2012 Report Share Posted May 2, 2012 Hi, until now I see lots of discussions on UVM for pre-simulation, which is without timing information extracted from backend. Is there any possibility that UVM supports post-simulation with timing information extracted after P&R? I guess it should because UVM is still systemverilog, but is there any detailed discusstion on it? Quote Link to comment Share on other sites More sharing options...
SeanChou Posted May 3, 2012 Report Share Posted May 3, 2012 UVM actually talks about testbenches, it does not really care which kind of DUT it is RTL/VHDL, C/C++/SC or in FPGA, evan in silicon. Seems to me there is no need to be discussed. Quote Link to comment Share on other sites More sharing options...
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