jithinraj1989 Posted April 21, 2012 Report Posted April 21, 2012 Hi, I am working on ovm to uvm migration. In my ovm environment run_test is called after 2us in the top module initial block. But when i give the same delay in uvm environment it is giving an error. "No non-zero delays are allowed before run_test()" I could find that there is a fatal error message in uvm library as follows:- -------------------------------------------------------------------------------- task uvm_root::run_phase (uvm_phase phase); if($time > 0) `uvm_fatal("RUNPHSTIME", {"The run phase must start at time 0, current time is ", $sformatf("%0t", $realtime), ". No non-zero delays are allowed before ", "run_test(), and pre-run user defined phases may not consume ", "simulation time before the start of the run phase."}) endtask ---------------------------------------------------------------------------- I am using run_phase() in testcase. And I need to have some delays before I call run_test. Please suggest some solution. Thanks in advance. . Quote
janick Posted April 23, 2012 Report Posted April 23, 2012 > And I need to have some delays before I call run_test. Why? What happens before that point in time?? And why isn't it driven by UVM?? If you implement your tests in main_phase(), you are free to insert any delay before it begins. But the UVM testbench hierarchy should exists (and run) from the beginning of time. Quote
uwes Posted April 23, 2012 Report Posted April 23, 2012 uvm doesnt allow time being spend before run_test(). anything between run_test() and run_phase() basically builds the static infrastructure/topology - then real wall clock time is spend with the created instances. so please describe your use model and i'm this also fits into the uvm infrastructure Quote
aji.cvc Posted April 25, 2012 Report Posted April 25, 2012 Maybe it is an env ported from OVM? We have seen several users doing this in OVM - simply b'cos OVM allowed only one task - run(). Many simple designs need simple reset toggling before starting transactions, hence this was convenient (than doing a virtual sequence etc.). Maybe same reason with jithinraj1989 too? BTW - the fix above rationale in UVM would be to move the reset to reset_phase. Regards Ajeetha, CVC www.cvcblr.com/blog Quote
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