cschmitt Posted April 12, 2012 Report Share Posted April 12, 2012 Does the UVM register model have support for shadow registers? In my DUT there are a few registers that have shadows, ie. on a write the shadow register is written and this value is not transferred to the actual register until another event (in this case a third register gets written). As a result, the built-in bit bash test is failing because it thinks the actual register is not being written correctly: write(AREG, 3); -> writes 3 to AREG_SHADOW read(AREG, data); -> reads from AREG which still has the original value Quote Link to comment Share on other sites More sharing options...
petermonsson Posted May 1, 2012 Report Share Posted May 1, 2012 Hi, I see two options: 1) Declaring a RO and WO register sharing the same address (UVM User Guide section 5.7.5) 2) Declaring the register with NO_REG_TESTS In both cases you will want to verify the shadow functionality seperately. Best Regards Peter Quote Link to comment Share on other sites More sharing options...
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