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UVM Shadow Registers

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Does the UVM register model have support for shadow registers? In my DUT there are a few registers that have shadows, ie. on a write the shadow register is written and this value is not transferred to the actual register until another event (in this case a third register gets written). As a result, the built-in bit bash test is failing because it thinks the actual register is not being written correctly:

write(AREG, 3); -> writes 3 to AREG_SHADOW

read(AREG, data); -> reads from AREG which still has the original value

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