UVM Shadow Registers

[cschmitt]

Does the UVM register model have support for shadow registers? In my DUT there are a few registers that have shadows, ie. on a write the shadow register is written and this value is not transferred to the actual register until another event (in this case a third register gets written). As a result, the built-in bit bash test is failing because it thinks the actual register is not being written correctly:

write(AREG, 3); -> writes 3 to AREG_SHADOW

read(AREG, data); -> reads from AREG which still has the original value

[petermonsson]

Hi,

I see two options:

1) Declaring a RO and WO register sharing the same address (UVM User Guide section 5.7.5)

2) Declaring the register with NO_REG_TESTS

In both cases you will want to verify the shadow functionality seperately.

Best Regards

Peter