How to implement special registers?

[hhq]

Hi, I am new to SystemC language.

I know that register can be implemented by sc_signal,

but I wonder how to implement some special registers.

Can anyone give some examples?

 

1. Read clear register. Support both read and write, but upon read() is called,

the value is returned as sc_signal, and the register is set to zero.

If both read() and write() are called on the same cycle, write() has the priority to update the value.

 

2. Two module can both write the register, but module which contains the register has the priority if both write occurs on the same delta

 

3. write() to the register does not effect the value of register, but an event is triggered.

 

3. write() to the register always trigger an event, even if the value is not changed.

 

4. The bit31 of a 32bit register is always is 0, but write 1 to bit31 triggers an event

other bit does not trigger an event

[David Black]

1. Derive from sc_signal and overload the read method to call write before returning the previous value
2. That would be awkward because writes are not seen until the next delta cycle and there is no way to guarantee which process goes first. Processes are not differentiated on the basis of module when executed by the SystemC Kernel (and there is intentionally no mechanism to do so since it would violate the premises of event driven simulation.) I suppose you could setup a module based mapping and determine the owner during the update cycle. You could perhaps defer reads to block until the next delta cycle.
3. Derive from sc_signal and provide a new method to signal an event. Not sure how useful this is if you cannot write a value.
4. Same as #3

All of this requires you to have a deep understanding of the event-driven simulator kernel and be capable of writing your own primitive channels. You should thoroughly understand how sc_signal works.  You might find the following useful: https://github.com/dcblack/SystemC-Engine (or sign-up for Doulos' Fundamentals of SystemC course).

Notice that this is all simple behavioral modeling using C++ constructs. If you do not know C++ well, then you need to get educated. C++ is a relatively complex topic and you won't learn everything about it in a forum. Your best bet is to educate yourself: read a book, take a course and apply it.

 

 

[hhq]

Thanks. I have some software background, just confused by systemC code.

 

Another question:

How to implement a register which takes one cycle of specific frequency to update? (not delta)

 

For example,

A register which is in a clock domain of 100MHz.

and another register which is in a clock domain of 1000MHz.

[Eyck]

Do you mean register as in RTL (register-transfer-level) or regsiter in the sense of something read- and writable e.g. by a processor?

[hhq]

yes

[Eyck]

I assume yes means registers in the sense of read/write register like memory mapped peripheral registers.

In this case you would use some specialized implementation to model the behavior. One example would be the sc_register in the SystemC Component library (SCC) which can be found here: https://github.com/Minres/SystemC-Components/blob/5b65d825766dd2e5359230b0451a23edaeba8d29/src/components/scc/register.h#L74. This allows to hook it up e.g. with a TLM socket to model SW accesses and attach callbacks to model behavior. Some examples of this can be found here: https://github.com/VP-Vibes/VPV-Peripherals/tree/main/sifive where you may have a look at the CLINT (some kind of interrupt controller) in the files clint.h/.cpp and gen/clint_regs.h.