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Trying to compile my mixed vhdl/ SV-UVM code with vcs. dut is in vhdl and uvm testbench is in SV.

I am using the multi-step analyse/eloborate method and have problem here.

1) vhdlan -full64 -work work -file ${vhdl_f} -l compile.vcslog

-- works fine

2) vlogan -ntb_opts uvm-1.1 -full64 -work work -sverilog -lca -f ${filelist} -l compile.vcslog

reports this error:

Error-[sV-LCM-PND] Package not defined

my_pkg.sv, 141

my_pkg, "uvm_pkg::"

Package scope resolution failed. Token 'uvm_pkg' is not a package.

Originating module 'my_pkg'.

Move package definition before the use of the package.

3) vcs -full64 -work work -time_resolution 1ps +vpi +vcsd +memcbk -sverilog -lca -ntb_opts uvm-1.1 +define+UVM_TR_RECORD my_tb_top -l compile.vcslog

-- didn't reach here.

How can I fix these issues. BTW the same code works in IUS/irun.

Is there a single step analyse/elaborate method for compiling mixed hdl ?

What is the -lcs option here, I copied it from one of the examples.

Thanks for any help

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It is unlikely you will want to recompile UVM library everytime so the flow is designed for you to analyze UVM files once per project per VCS version.

Update your synopsys_sim.setup with the path to where you want to store your analyzed UVM_LIB

vhdlan -full64 -work work -file ${vhdl_f} -l compile.vcslog

vlogan -q -ntb_opts uvm-1.1 -full64 -work UVM_LIB -sverilog

vlogan -q -ntb_opts uvm-1.1 -full64 -work work -sverilog -f ${filelist} -l compile.vcslog

vcs -full64 -time_resolution 1ps +vpi +vcsd +memcbk -sverilog -ntb_opts uvm-1.1 my_tb_top -l compile.vcslog -debug_all

./simv +UVM_TESTNAME=foobar_test -gui

If you have any problem then please email vcs_support@synopsys.com



Edited by adielkhan
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Thanks for the prompt reply and helpful suggestion.

A small correction for your suggestion, in case anyone looks at this thread for help.

The second vlogan should include the uvm src path:

vlogan -full64 -work work -sverilog +incdir+${UVM_HOME}/env/uvm-1.1 -f ${filelist} -l compile.vcslog

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