Verilog AMS netlist needs to be wrapped by a verilog AMS file.

[prase]

Hi Team, 

I want to use a verilog AMS wrapper to wrap my orginal verilog ams netlist because the input that is driven has 3 parts, amplitude, phase and frequency. But my analog circuit has only 1 input as signal input. So I want to use this wrapper to generate a sine wave and feed as input to my circuit. 

 assign  bbmux_lp_n_ai = offset + (bbmux_lp_n_ai_amplitude * $cos(2*pi*bbmux_lp_n_ai_frequency*$abstime));

I am genrating this in my wrapper and driving it like this

  rxbb_lp rxbb_lp_inst(
    .VDD1V8BB(VDD1V8BB) ,
    .VSS1V8A(VSS1V8A) ,
    .VSS1V8BB(VSS1V8BB) ,
    .VSS_SUB(VSS_SUB) ,
    .bbmux_lp_n_ai(bbmux_lp_n_ai) ,...

 

where rxbb_lp is my vams netlist. 

Is this possible ? since right now I am getting errors when I do this as "of design unit 'rxbb_lp' is unresolved in 'reference_library.rxbb_lp_wrapper:vams'."

Any help would be very useful!

Thank you

 

[Martin Barnasconi]

This forum discusses SystemC-AMS, not Verilog-AMS. Please contact your EDA tool provider to answer your Verilog-AMS specific questions.