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Found 2 results

  1. Hi Team, I want to use a verilog AMS wrapper to wrap my orginal verilog ams netlist because the input that is driven has 3 parts, amplitude, phase and frequency. But my analog circuit has only 1 input as signal input. So I want to use this wrapper to generate a sine wave and feed as input to my circuit. assign bbmux_lp_n_ai = offset + (bbmux_lp_n_ai_amplitude * $cos(2*pi*bbmux_lp_n_ai_frequency*$abstime)); I am genrating this in my wrapper and driving it like this rxbb_lp rxbb_lp_inst( .VDD1V8BB(VDD1V8BB) , .VSS1V8A(VSS1V8A) , .VSS1V8BB(VSS1V8BB) , .VSS_SUB(VSS_SUB) , .bbmux_lp_n_ai(bbmux_lp_n_ai) ,... where rxbb_lp is my vams netlist. Is this possible ? since right now I am getting errors when I do this as "of design unit 'rxbb_lp' is unresolved in 'reference_library.rxbb_lp_wrapper:vams'." Any help would be very useful! Thank you
  2. Hi there, I am currently trying to simulate SystemC-AMS models with Incisive and Verilog-on-top. For this purpose I have written a Verilog-AMS wrapper and at first tried to simulate a simple SystemC model with the following ports: #include <systemc> SC_MODULE(my_mod) { sc_in<double> sig_in; sc_out<double> sig_out; ... }; The VAMS wrapper basically looks as follows: `include "disciplines.vams" `timescale 1ns/1ns module my_mod_wrapper (in_if, out_if); input in_if; wreal in_if; output out_if; wreal out_if; real out_ext_temp; reg[63:0] in_ext; wire[63:0] out_ext; assign out_if = out_ext_temp; initial begin in_ext = $realtobits(in_if); end always @(in_if) in_ext = $realtobits(in_if); always @(out_ext) out_ext_temp = $bitstoreal(out_ext); my_mod my_mod_inst(.sig_in(in_ext), .sig_out(out_ext)); endmodule module my_mod(sig_in, sig_out) (* integer foreign = "SystemC"; *); input[63:0] sig_in; logic[63:0] sig_in; output[63:0] sig_out; logic[63:0] sig_out; endmodule However, when changing the port types of my_mod from ... sc_in<double> sig_in; sc_out<double> sig_out; ... to ... #include <systemc-ams.h> ... sca_tdf::sca_in<double> sig_in; sca_tdf::sca_out<double> sig_out; ... in order to have SystemC-AMS ports, the simulator gives the following error message: ncelab: *E,SCK923: No valid SystemC port found in exported SystemC module that matches with HDL port in corresponding shell HDL module: Module name is 'my_mod' Instance name is 'top.my_mod_wrapper_inst.my_mod_dut' Port name is 'sig_in' In file: sc_cosim.cpp:4969. ncelab: *E,SCK954: Error connecting port of SystemC module instantiated in HDL: Module name is 'my_mod' Port name is 'sig_in' In file: sc_cosim.cpp:1446. ncelab: *F,SCIPCF: Could not connect port 'sig_in' for instance 'top.soc_wrapper_inst.my_mod_dut'. irun: *E,ELBERR: Error during elaboration (status 2), exiting. make: *** [run] Error 1 So it seems I cannot simply use this way of connecting double ports to reg/wire types, although sig_in and sig_out are from type double in both cases. What is the best way to connect SystemC-AMS modules to Verilog(-AMS) in my case? Cheers, Seb
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