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Found 8 results

  1. Hi Team, I want to use a verilog AMS wrapper to wrap my orginal verilog ams netlist because the input that is driven has 3 parts, amplitude, phase and frequency. But my analog circuit has only 1 input as signal input. So I want to use this wrapper to generate a sine wave and feed as input to my circuit. assign bbmux_lp_n_ai = offset + (bbmux_lp_n_ai_amplitude * $cos(2*pi*bbmux_lp_n_ai_frequency*$abstime)); I am genrating this in my wrapper and driving it like this rxbb_lp rxbb_lp_inst( .VDD1V8BB(VDD1V8BB) , .VSS1V8A(VSS1V8A) , .VSS1V8BB(VSS1V8BB) , .VSS_SUB(VSS_SUB) , .bbmux_lp_n_ai(bbmux_lp_n_ai) ,... where rxbb_lp is my vams netlist. Is this possible ? since right now I am getting errors when I do this as "of design unit 'rxbb_lp' is unresolved in 'reference_library.rxbb_lp_wrapper:vams'." Any help would be very useful! Thank you
  2. Dear reader, I recently started exploring SystemC and SystemC AMS. I'm working through this presentation/tutorial by TU Delft. I'm trying to connect two SCA_TDF modules through a sca_tdf::sca_signal to build the Binary Amplitude Shift Keying modulator. In the constructor of my 'transmitter' I creating two instantiations of a 'mixer' and a 'sine'. mix = new mixer("mixer", rate ); mix->in_bit(in); mix->carrier(wave); mix->mixed(out); sin = new sine("sin", freq, rate ); sin->out(wave); Whereas signals, ports and pointers of this transmitter are defined as follows: sca_tdf::sca_in<bool> in; sca_tdf::sca_out<double> out; mixer * mix; sine * sin; sca_tdf::sca_signal<double> wave; The ports of the mixer are as follows: sca_tdf::sca_in<bool> in_bit; sca_tdf::sca_in<double> carrier; sca_tdf::sca_out<double> mixed; And the port of the sine is as follows: sca_tdf::sca_out<double> out; When I compile and run this, the following message appears: Error: SystemC-AMS: sca_tdf::sca_signal has no driver the following modules are connected to the channel: transmit.mixer In file: ../../../../../src/scams/impl/synchronization/sca_synchronization_alg.cpp:256 I'm pretty sure I've connected this channel (as shown above). Does anyone know what this problem actually means and how I can resolve it? Solved A module that had a sca_out port was inherited from standard SystemC module (SC_MODULE) instead of AMS module (SCA_TDF_MODULE).
  3. Hello All, I am new to AMS modeling & I have been going through some study material related to Verilog-A/Verilog-AMS. I have a few questions related to AMS. I hope members here will comment. 1) Is AMS always needed when there is a mix of digital & analog modules in a design. For example, can it not be used for pure Analog modeling when I would like to have abstract analog models? 2) In most of the references, AMS is mentioned as an approach to model design blocks. In my view, AMS has to be used for creating testbench for such blocks. For example, if my design has analog interface then I have to use AMS to apply stimuli to that interface or use AMS to process output from that interface. Thanks,
  4. Hello everybody, I would like to know if AMS and SystemC have two different schedulers. If yes then how do they interact? Moreover i would like to ask how many extensions does SystemC has? Thanks in advance
  5. Hi, I am currently considering to enhance a virtual prototype TLM model with AMS models mainly in order to add more accurate models of the power management part including accurate battery model, voltage regulator control loops... We have stringent simulation performance criteria for the virtual prototype since it needs to run SW on a complex HW model. If we just use simple ams2de ports to interface the tlm part with the AMS model we risk to brake the whole VP simulation. I am missing some guide to properly define the interface between the AMS part and the TLM part. I found attached screenshot from SystemC AMS extension - alignment with SystemC-TLM Workshop slides which depicts an approach to define that interface. However I am not so clear about how it can be implemented. The question here is: Is there any implementation guide or source code template for a simple example on how to define the interface between AMS and TLM? @Martin: I would really appreciate any hint ! Many thanks! Ismael, systems engineer big semiconductor company
  6. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that this may be harder for the simulation. So, any ideas? Is there any sc_pause? I know that there is a sc_halt, but it looks like it works only with threads, which would not be suitable to be called from an AMS module. Thanks a lot! ;-)
  7. Hi everyone, I have been working with SystemC-AMS lately and having nice results, but now I'm facing some issues with the sca_eln::sca_tdf::sca_vsink module. I created some sc_modules with ELN modules inside. Quite briefly, the final electrical network (which I get from putting those sc_modules together) that I have been having problems with is: ELN: node_ref -> vsource -> node -> vsink -> node -> r -> node -> vsink -> node -> r -> node_ref SC :|-----GENERATOR-----|->|-----------PIPE-----------|->|----------PIPE------------| -> |---SINK---| If understood correctly the sca_eln::sca_tdf::sca_isink module is like a voltage source with v = 0 V, so they should not be connected in parallel. I do not know if the vsink works in a similar way, being a current source, so there should not be two connected in a row. Taking a look at the Users guide it is noted for both modules that "No equation added to the equation system", so I'm not sure if this is a conflict because of what I just mentioned. The error I'm getting is: I would like to know the reason why this is not working, if anyone happen to find any The idea of having vsink's there is because I want to send the value from the electrical network in that spot to a TDF module. I'm not sure if this is ok or is a crazy idea. I hope I explained everything clearly, otherwise, just ask and I'll try to do it better Thanks a lot! Kike
  8. Hi, I got some problems with the systemc ams library, and came to a point where i run out of ideas what to do, where to search for solutions... I try to learn systemc-ams, and therefore i don't know too much about it yet, but i got some normal systemc examples done. Now i tried to do something with the ams-extension but i got following compile error: make all Building target: caes Invoking: GCC C++ Linker g++ -L/home/mks/systemc/systemcams/lib-linux -L/home/mks/systemc/systemc/lib-linux -o "caes" ./sine/main.o ./shiftreg/main.o ./lfsr/main.o ./first_counter/first_counter.o ./first_counter/first_counter_tb.o ./fifo-int-3/main.o ./fifo-int-2/main.o ./fifo-int/main.o ./cordic/main.o -lsystemc-ams -lsystemc /usr/bin/ld: error: /home/mks/systemc/systemcams/lib-linux/libsystemc-ams.a(sca_implementation_info.o): incompatible target sca_vcd_trace.cpp:470: error: undefined reference to 'sca_core::sca_version()' collect2: ld gab 1 als Ende-Status zurück make: *** [caes] Fehler 1 Anyone knows what to do about this? regards mks
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