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Found 7 results

  1. Dear reader, I recently started exploring SystemC and SystemC AMS. I'm working through this presentation/tutorial by TU Delft. I'm trying to connect two SCA_TDF modules through a sca_tdf::sca_signal to build the Binary Amplitude Shift Keying modulator. In the constructor of my 'transmitter' I creating two instantiations of a 'mixer' and a 'sine'. mix = new mixer("mixer", rate ); mix->in_bit(in); mix->carrier(wave); mix->mixed(out); sin = new sine("sin", freq, rate ); sin->out(wave); Whereas signals, ports and pointers of this transmitter are define
  2. Hello All, I am new to AMS modeling & I have been going through some study material related to Verilog-A/Verilog-AMS. I have a few questions related to AMS. I hope members here will comment. 1) Is AMS always needed when there is a mix of digital & analog modules in a design. For example, can it not be used for pure Analog modeling when I would like to have abstract analog models? 2) In most of the references, AMS is mentioned as an approach to model design blocks. In my view, AMS has to be used for creating testbench for such blocks. For example, if my design has analog
  3. Hello everybody, I would like to know if AMS and SystemC have two different schedulers. If yes then how do they interact? Moreover i would like to ask how many extensions does SystemC has? Thanks in advance
  4. Hi, I am currently considering to enhance a virtual prototype TLM model with AMS models mainly in order to add more accurate models of the power management part including accurate battery model, voltage regulator control loops... We have stringent simulation performance criteria for the virtual prototype since it needs to run SW on a complex HW model. If we just use simple ams2de ports to interface the tlm part with the AMS model we risk to brake the whole VP simulation. I am missing some guide to properly define the interface between the AMS part and the TLM part. I found attache
  5. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that thi
  6. Hi everyone, I have been working with SystemC-AMS lately and having nice results, but now I'm facing some issues with the sca_eln::sca_tdf::sca_vsink module. I created some sc_modules with ELN modules inside. Quite briefly, the final electrical network (which I get from putting those sc_modules together) that I have been having problems with is: ELN: node_ref -> vsource -> node -> vsink -> node -> r -> node -> vsink -> node -> r -> node_ref SC :|-----GENERATOR-----|->|-----------PIPE-----------|->|----------PIPE------------| -> |---SINK---| I
  7. Hi, I got some problems with the systemc ams library, and came to a point where i run out of ideas what to do, where to search for solutions... I try to learn systemc-ams, and therefore i don't know too much about it yet, but i got some normal systemc examples done. Now i tried to do something with the ams-extension but i got following compile error: make all Building target: caes Invoking: GCC C++ Linker g++ -L/home/mks/systemc/systemcams/lib-linux -L/home/mks/systemc/systemc/lib-linux -o "caes" ./sine/main.o ./shiftreg/main.o ./lfsr/main.o ./first_counter/first_counter.o ./fi
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