Jump to content

Martin Barnasconi

  • Content Count

  • Joined

  • Last visited

  • Days Won


Everything posted by Martin Barnasconi

  1. Yes, many publications have been posted on this during the last decade. Check IEEEEXplore for the papers. Another approach is check publications from DOCEA POWER, a company which was focusing on this, and is still active in this domain (although under a different name)
  2. Accellera released the SystemC AMS user's guide application examples, which are available for download via this link. These examples can be executed using your preferred EDA tools, as long as they support the SystemC and SystemC AMS language standard. Alternatively, you can use the open source SystemC and SystemC AMS reference implementations. Instructions for installation and execution can be found in the INSTALL or README files as part of these packages. We welcome your feedback!
  3. The SystemC AMS standard defines in section (sca_util::sca_trace) that it can trace objects of type sca_traceable_object. Since all ELN primitives are derived of this type, you can simply trace the ELN component itself, see example below SC_MODULE(eln_circuit) { // node declaration sca_eln::sca_node n1; // ELN node sca_eln::sca_node_ref gnd; // ELN ground // component declaration sca_eln::sca_vsource vin; sca_eln::sca_r r1; // constructor including ELN netlist eln_circuit( sc_core::sc_module_name nm ) : vin("vin", 0.0, 1.23), r1("r1", 1e3) { // Only ELN primitives requires explicit timestep assignment to one element vin.set_timestep(1.0, sc_core::SC_MS); // netlist vin.p(n1); vin.n(gnd); r1.p(n1); r1.n(gnd); } }; int sc_main(int argc, char* argv[]) { eln_circuit cir("eln_circuit"); sca_util::sca_trace_file* tf = sca_util::sca_create_tabular_trace_file("trace.dat"); sca_util::sca_trace(tf, cir.n1, "v_n1"); sca_util::sca_trace(tf, cir.vin, "i_through_vin"); sca_util::sca_trace(tf, cir.r1, "i_through_r1"); sc_core::sc_start(1.0, sc_core::SC_MS); sca_util::sca_close_tabular_trace_file(tf); return 0; }
  4. The 2020 edition of the SystemC AMS user's guide is available here https://www.accellera.org/downloads/standards/systemc
  5. The Accellera SystemC AMS Working Group released the 2020 edition of the SystemC AMS User's Guide. You will find the user's guide on this page: https://www.accellera.org/downloads/standards/systemc This version of the user's guide is fully compatible with the SystemC AMS standard released as IEEE Std. 1666.1-2016. It describes all the features introduced in the SystemC AMS language standard during the last decade. For example, the user’s guide now explains the use of the dynamic timed data flow capabilities, to make AMS system simulations even more efficient and running even faster. The SystemC AMS Working Group is currently preparing the release of the user's guide application examples as separate download. Availability of these application examples will be communicated at a later stage. Please use this forum to post your questions or remarks on the user's guide.
  6. The code snippet listed above shows that the file is repeatedly opened in the processing() method, since this method is called at each time step. Instead, the file should only be opened once, e.g. in the module constructor or initialize() callback. Note that in this case you need to make the variable of type ifstream a (private) member of the class, so other methods can access this variable.
  7. Indeed, the Accellera SystemC AMS working group is currently active in updating the SystemC AMS user's guide, including an detailed explanation of the dynamic TDF features introduced since SystemC AMS 2.0 (and also incorporated in the IEEE 1666.1 standard) and obviously removing deprecated methods. Examples have been presented in various workshops and tutorials given the last decade at DATE, DVCon Europe, DAC conferences. Please check the SystemC AMS community pages for some of the links. https://accellera.org/community/systemc/about-systemc-ams The "golden reference" for SystemC AMS documentation is actually the IEEE 1666.1 standard itself. Although it might require some practice to understand all the formal definitins and terms, it well explains the underlying concept and the modeling capabilities of the language. The standard can be found here, and thanks to Accellera you can download a copy via the IEEE Get Program here: https://standards.ieee.org/standard/1666_1-2016.html It is well known that SystemC AMS is much faster than Simulink. Actually I consider your 20x speed improvement rather modest, probably since your design is relatively small (this also holds for most of the academic papers I've seen). My observation is that bigger systems in SystemC-AMS show an even bigger speed difference in favor of SystemC-AMS.
  8. The (old) SystemC AMS User's Guide is now directly accessible via this link: http://www.accellera.org/images/downloads/standards/systemc/OSCI_SystemC_AMS_Users_Guide.pdf And also listed in the overview of SystemC standards: http://www.accellera.org/downloads/standards/systemc As mentioned before, the AMS Working Group members are currently working on the update of the User's Guide by including the dynamic TDF timestep features which are also part of the IEEE 1666.1 standard.
  9. Please note that the electrical primitives are predefined elements using the ELN model of computation; there is no mechanism to create your own electrical primitives. As such there is no such thing as a SCA_ELN_MODULE. Primitive modules can only be created for the TDF MoC, hence the SCA_TDF_MODULE macro as alternative to the class sca_tdf::sca_module. Wrt the the SystemC AMS 1.0 User's Guide, I will start an action to make it available independently of the LRM. Although the authors of the User's Guide are quite busy with other things, they full recognize the need to update the guide including the Dynamic TDF features as introduced in AMS 2.0 and IEEE1666.1. We hope to announce an update of the document in the coming period.
  10. It looks like you have a multi-rate system, i.e. somewhere you defined a <port>.set_rate(..) in a set_attributes callback. Now you try to access the n-th sample at this port, like <port>.read(<sample>), but the nth sample is higher than the rate specified. This means you have either the wrong rate, or reading a sample outside the range defined by the rate.
  11. My advice is to ask your EDA vendor for support. If they are not able to support you, then download the SystemC-AMS open source implementation yourself and compile it against a commercial SystemC-based simulator. After that create your (complex) design and show the simulation benefits to your EDA vendor, and explain (again) why SystemC-AMS is essential to have.
  12. RNM is a simple approach to represent analog signals by a real-value (amplitude) on a (discrete) event driven time axis. Depending on the type of signal, you need to generate a lot of samples (events) to follow the shape of the waveform (i.e. Nyquist rule). The event scheduling in a digital solver results in some simulation overhead, because the event list is dynamically scheduled and executed. The more events, the slower the simulation. Especially when you start modeling RF systems in RNM, your system simulation will get slow. In addition, the more input and outputs, the more events at these inputs and outputs, which need to be added to the sensitivity-list of the discrete-event solver. So the bigger the RNM system, the slow its gets. Thanks to the Dataflow based simulation concept in SystemC-AMS, we do not have these issues. In SystemC-AMS the dataflow graph is based on the interconnected TDF modules, and computed before simulation starts. For each time step, this graph is executed only once, including signal input/output updates for all associated TDF modules. As such, the size of the TDF system does not matter much. Especially for bigger systems you will clearly see a difference between RNM in Verilog-AMS or SystemVerilog versus TDF modeling in Systemc-AMS, the latter being much faster.
  13. Thanks for reporting this issue. We will look into this. Just to be clear, I guess you refer to the example which is part of the crave version 0.9-alpha ?
  14. UVM-SystemC simulation will automatically finish if all UVM phases have been executed (without any pending objections). You can look in the examples/simple/objections/basic example how to get the objection count. I expect somewhere you raise an objection, but you do not drop it. The SystemC sc_stop will trigger end_of_simulation. So this is expected behaviour. However, in UVM-SystemC you should not call sc_stop yourself (in a similar way, as a user you do not start the simulation with sc_start)
  15. The xutility and the _Adopt method you mentioned are not from the SystemC-AMS library. Who is calling this function? Perhaps you can send a backtrace.
  16. Some remarks/questions: Please try the latest 2.1 version, which can be found here: http://www.coseda-tech.com/systemc-ams-proof-of-concept Can you supply some additional information on the compiler you use on windows: is this gcc in mingw/cygwin or using the msvc compiler. Please supply version Did you try starting the execution using gdb? Is your design using TDF modules only or also LSF and/or ELN?
  17. This could be caused by the famous CRLF incompatibility between Windows/Dos and Unix/Linux. Please try to run dos2unix for all files in the entire systemc tree, and then try again.
  18. This is not a UVM-SystemC library but Eclipse configuration issue. Some things you could check: In the Project Explorer view, the project should be labeled as C/C++ project and contain a subdirectory "Includes". In this list you should see the cygwin and uvm-systemc include directories. If this is not the case, then your project properties are not well defined. Do a Index >> Rebuild Just build the example and see if the error disappear (such build also does start a reindexing Also note that UVM-SystemC puts all classes in the uvm namespace. This means you should explicitly prefix with uvm:: or define a using namespace uvm (only inside method implementations, not in global scope of header files)
  19. There are some commercial and proprietary functional coverage approaches in C++/SystemC, but these are not contributed for standardization. Therefore the WG will work on a new and open standard proposal, along the lines of the initial ideas as presented at NASCUG at DAC2014 (slide 30, 31): http://nascug.org/events/20th/1-NASCUG20-UVMforSystemC-Karsten.pdf Of course this is subject to change. For example, the prefixes will change, as well as some methods and arguments, since we aim for integration in UVM-SystemC.
  20. I expect your SystemC module, as leave cell, uses regular ports (sc_in/sc_out). The SystemC AMS TDF module should use the converter ports (sca_tdf::sca_de::sca_in, sca_tdf::sca_de::sca_out), so it can be connected to regular SystemC modules. This means that the top-level module, which instantiates this SystemC module and the SystemC AMS TDF module, should then a sc_signal, since the input for the SystemC AMS TDF module needs to see this type of signals.
  21. The SystemC AMS 2.1 proof-of-concept in indeed licensed under Apache License, Version 2.0, January 2004. Distribution need to comply to the rules as defined in this Apache 2.0 license. Your package website indeed mentions under license "custom:SystemC-AMS Open Source License". Instead it should state "Apache License Version 2.0, January 2004". My advice is to also contact the developer/maintainer of the PoC, which is COSEDA Technologies GmbH, to inform them on this initiative and to confirm your packaging initiative is recognized/supported: http://www.coseda-tech.com/ info@coseda-tech.com
  22. In your State-space function you did not explicitly specify the time step. In such case, the State-space function will take the module time step. It could be that this module time step is too coarse for your analog State-space equation. In that case, you should specify a more fine-grained timestep as argument for the State-space function.
  23. This is work-in-progress in the Accellera SystemC Verification Working Group. Too difficult to give any estimations on availability, but I suggest to watch for the announcements around Accellera's DVCon events planned later this year. Accellera member companies are encouraged to join the working groups to help in the creation, testing and debug of these important functionalities.
  24. Could you please check with SystemC AMS 2.1 PoC and report if the warning is still there? http://www.coseda-tech.com/systemc-ams-proof-of-concept
  25. The SystemC class library itself does not support this configuration functionality. The UVM-SystemC class library obviously adds this functionality, since we target exactly the same functionality and features as UVM-SystemVerilog.
  • Create New...