Nithin 0 Posted January 9 Report Share Posted January 9 Hi, Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets? Thanks in advance. Regards, Nithin Quote Link to post Share on other sites
David Black 181 Posted January 9 Report Share Posted January 9 Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.). Quote Link to post Share on other sites
basarts 4 Posted January 11 Report Share Posted January 11 In addition, if your SystemC model contains ports of type double, you need to convert them in the test harness to 64 bit vectors first. Quote Link to post Share on other sites
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