Nithin Posted January 9 Report Share Posted January 9 Hi, Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets? Thanks in advance. Regards, Nithin Quote Link to comment Share on other sites More sharing options...
David Black Posted January 9 Report Share Posted January 9 Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.). Quote Link to comment Share on other sites More sharing options...
Bas Arts Posted January 11 Report Share Posted January 11 In addition, if your SystemC model contains ports of type double, you need to convert them in the test harness to 64 bit vectors first. Quote Link to comment Share on other sites More sharing options...
Nithin Posted April 6 Author Report Share Posted April 6 Hi, Thank you David and "basarts" One follow up question on this. I found that it is possible to use SYSCAN to instantiate C-models in RTL testbench and do VCS simulation. Unfortunately SYSCAN is having some issues with latest version of VCS. I am wondering if there is some way to get rid of SYSCAN and use some other method to run VCS simulation in RTL testbench with C-model instantiation. Thanks in advance. Regards, Nithin Quote Link to comment Share on other sites More sharing options...
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