Verifying SystemC model with Verilog/SV testbench

[Nithin 0]

Hi,

Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets?

 

Thanks in advance.

Regards,

Nithin

[David Black 185]

Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.).

[Bas Arts 4]

In addition, if your SystemC model contains ports of type double, you need to convert them in the test harness to 64 bit vectors first.

[Nithin 0]

Hi,

Thank you David and "basarts"

One follow up question on this. I found that it is possible to use SYSCAN to instantiate C-models in RTL testbench and do VCS simulation. Unfortunately SYSCAN is having some issues with latest version of VCS. I am wondering if there is some way to get rid of SYSCAN and use some other method to run VCS simulation in RTL testbench with C-model instantiation.

Thanks in advance.

Regards,

Nithin