Verifying SystemC model with Verilog/SV testbench

[Nithin 0]

Hi,

Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets?

 

Thanks in advance.

Regards,

Nithin

[David Black 181]

Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.).

[basarts 4]

In addition, if your SystemC model contains ports of type double, you need to convert them in the test harness to 64 bit vectors first.