array of pointer to sc_fifo

[GUEST]

Hi,

I want to create an array of pointers to sc_fifo <unsigned int> (I get the size of each fifo during the simulation).

I tried to write:

sc_vector < sc_fifo <unsigned int> *> FIFOS;

in the ctor:    FIFOS.init(5);

and in another function make a dynamic memory allocation to each sc_fifo in the vector,

but it did not work, how can I write this?

Thanks

 

[David Black]

I don't think sc_vector supports non-sc_object types (pointers are not sc_object's). Maybe you should describe your use-case first, so we can make some sensible solutions.

 

[GUEST]

I need to create an array of FIFOS.

The size of each FIFO is an input and is different from one to another

[shivambhatele]

You can check this thread https://stackoverflow.com/questions/42917674/sc-fifo-write-first-chance-exception, Someone putted same query.

[David Black]

@GUESTWhen you say the size of each FIFO is an input, do you mean to say that during simulation the maximum legal size of the FIFO's is a dynamically changing input? Or is it the case that each FIFO is a different maximum size that is determined at statically at time zero before the simulation gets beyond the elaboration phase? Your answer to this has a critical impact to the response. sc_fifo is a static hardware feature and the nature of hardware is that it may not be changed after fabrication (elaboration is the simulator terminology). If you are looking to model varying software inputs, you may be using the wrong structure. Perhaps you could use a tlm_fifo or you need to use a C++ fifo or a std::queue<T>. All of these are valid modeling ideas for SystemC.

[GUEST]

I mean that the maximum legal size of each FIFO in the array is a dynamically changing input per simulation -

I get the inputs (sizes) once during simulation , set the FIFOS once and don't change them again during simulation.

(I need to model a structure that is managed as FIFO so sc_fifo gives me all the features I need)

[GUEST]

@David BlackThank you for your answer! I understood the problem.

can you help me to understand this code?

I saw in you wrote here   :   https://forums.accellera.org/topic/10-error-e113-insert-primitive-channel-failed-simulation-running/

"Any of your module has attempted to create an instance of a primitive channel (sc_signal, sc_fifo, etc) after the start of simulation.In systemC primitive channels can only be created before the start of simulation ."

So how can it be that the given code allocates memory to FIFO in main?