Error: (E113) insert primitive channel failed: simulation running

[WangYuchen]

Hello all,

I am going to build a four-MIPS platform by SystemC TLM2.0.

The purpose for that platform:

1. capture pcap dump file and preload into data memory;

2. load OpenDPI program into program memory;

3. trigger the MIPS processor on and simulate the performance.

I built a module called "Loader_Scheduler" which is used to capture packets in sequence and preload the data of each packet into different data memories.

The whole story is like, capture first packet and run the MIPS simulation, in the meantime, "Loader_Scheduler" will capture the second packet.

But I encountered such error:

Error: (E113) insert primitive channel failed: simulation running
In file: sc_prim_channel.cpp:166
In process: top.loader_scheduler.loader_scheduler @ 0 s
Finished sc_main.

I googled it:

Error: (E113) insert primitive channel failed: simulation running
In file: ../../../../src/sysc/communication/sc_prim_channel.cpp:166
Any of your module  has attempted to create an instance of a primitive channel (sc_signal, sc_fifo, etc) after the start of simulation.In systemC primitive channels can only be created before the start of simulation .
Please search your code for any signal declaration inside a function.

Does it mean I cannot let Loader_Scheduler run after the simulation start? Could you provide me any suggestions to solve it by loop or something else?

Thank you!

[Philipp A Hartmann]

It just means, what you already quoted:

Any of your module has attempted to create an instance of a primitive channel (sc_signal, sc_fifo, etc) after the start of simulation.In systemC primitive channels can only be created before the start of simulation .

Please search your code for any signal declaration inside a function.

You can use your Loader_Scheduler, you just can't create new signals (or other primitive channels) dynamically during simulation.

[David Black]

WangYuchen,

I am just adding to Philipps comment...

Perhaps you do not understand the difference between channels (e.g. primitive channels such as sc_signal<T> or sc_fifo<T>) and data types (e.g. int or double). Channels represent hardware behaviors. In SystemC, hardware is only allowed to be declared and constructed before simulation begins during the "elaboration phase". Channels are used to transfer data between processes. They are NOT containers (e.g. array, struct or std::vector<T>). Thus sc_signal<int> is not a new type of data, but rather it specifies hardware that is able to safely transfer data between processes.

[WangYuchen]

Thank you, Philipps and David!

Actually, I have finished all the Initialization in Constructor.

such as:

{
loader_scheduler = new Loader_Scheduler("loader_scheduler");

// bind sockets for router and loader_scheduler
cpu0.hwint0.write(loader_scheduler->hwint0);
cpu1.hwint1.write(loader_scheduler->hwint1);
cpu2.hwint2.write(loader_scheduler->hwint2);
cpu3.hwint3.write(loader_scheduler->hwint3);
......
}

In the loader_scheduler module:

switch (count % 4)
{
case 0:
memcpy ( ptr_data0_global, callback_result->packet, (int)(callback_result->header).len );
hwint0.write(true);
hwint1.write(false);
hwint2.write(false);
hwint3.write(false);
break;
......
}

I don't think it create any new instances during simulation only by changing the value of sc_signal.

Jump out of the creating new instances topic, let's thinking about the concept of this work:

1. first packet comes, load into Datamemory0 and trigger on Processor0

2. second packet comes, load into Datamemory1 and trigger on Processor1 (Procesor0 is still WORKING)

......

How can I achieve this target in the sc_main()?

sc_main() is a kind of this structure:

int sc_main (int argc, char *argv[] )
{
   const char  *app;
   char* pcap_file;
   icmIgnoreMessage("ICM_NPF");
   TopLevel_Mips32_TLM2_0 top("top");    //instantiate example top module

   // Allow different files to be loaded on command line
   if (argc > 1)
   {
app = argv[1];
pcap_file = argv[2];
pcap_file_global = pcap_file;
   }
   // pass the data memory address for preloading
   ptr_data0_global=top.data0.getMemory()->get_mem_ptr();
   ptr_data1_global=top.data1.getMemory()->get_mem_ptr();
   ptr_data2_global=top.data2.getMemory()->get_mem_ptr();
   ptr_data3_global=top.data3.getMemory()->get_mem_ptr();
   // Use the TLM shared memory. It needs to be loaded with the program.
   unsigned char *targetshPtr = top.program.getMemory()->get_mem_ptr();
   top.cpu0.loadNativeMemory(targetshPtr, 0x10000, 0x80080000, "program", app, 0, 1, 1);

   sc_core::sc_start(); // start the simulation
   cout << "Finished sc_main." << endl;
   return 0;  // return okay status
}

Preloading finishes before sc_start, simulation starts after sc_start. How can I achieve multiple simulations which start at different timespots.

Sorry for posting so many things. I have no idea how to build the body of codes ( sc_main() ), and I could assume "the Error: (E113) insert primitive channel failed: simulation running" could be solved if I have a more clear structure.

Thank you very much.

[apfitch]

Regarding your E113 error, the message points to "top.loader_scheduler.loader_scheduler" - so search in that code for creation of primitive channels.

Regarding your second issue, it's easiest to have all processes running all the time, and then delay the start of each processor model's processing I think - if I've understood what you want to do. I.e. have your MIPS models in some kind of idle loop until you want them to start.

There isn't an easy way to restart simulation. You can however call sc_start multiple times, so perhaps you could do

sc_start(1, SC_MS);

// start processor 2

sc_start(1, SC_MS);

//start processor 3

etc.

As I say, your model sounds complicated to an outside!

regards

Alan

[WangYuchen]

Thank you, Alan.

I fully agree with what you said. To put the processor into idle loop and use an interrupt handler to trigger on. The body of source code I have given is just a general assumption...

I already found the error of ERROR[113]. Because in loader_scheduler module, I made a terrible mistake that I defined hwint0-3 as sc_signal<> which were supposed to be sc_inout<>. That means, I didn't connect loader_scheduler to each MIPS processor.

Thank you very much.